Closed scorbetta closed 3 months ago
@scorbetta Can you provide the RTL of your design?
Sure thing. I'm attaching the OpenLANE config file as well. I had to remove the runs
folder due to space.
LAYER.tar.gz
@kareefardi Any idea?
@scorbetta Sorry I have been a bit busy this week. I am checking it out now.
@scorbetta These warnings are generated when each file is read before analyzing the hierarchy. If you consider HL_NEURON
by itself, it's default parameter value doesn't account for the out of bounds signal.
The whole system wouldn't be affect by this warning however I think it's best if you fix it inside the module itself to avoid future problems when reusing the module.
@kareefardi Got it. I can live with them then, however is this really how it should properly work? I mean, when I synthesize multiple Verilog files that belong to a given hierarchy, I would expect the top-level to forward values to the lower levels within the hierarchy. Otherwise there is no point to get a top with fixed parameters. And indeed that's how commercial tools do.
@scorbetta I think we may be able to do that with -defer
in Yosys when reading the Verilog files but this requires discussion internally on whether we want to do that. I will keep this issue open and update it.
@kareefardi Indeed that's what I did. I am now using a patched synth.tcl
script for synthesis. I added the -defer
option to the read_verilog
commands, and placed a hierarchy -check -top $vtop
command later. Warnings go away.
Description
I keep having the following warnings from the synthesis phase:
This points to a signal named
weights
defined as follows in the referenced file:NUM_INPUTS
andWIDTH
parameters get values from the top-level. The top-level has the following default values:So that
weights
has actual dimension of 128 bits. Meaning the warning above is wrong. Strangely, the synthesis outputresults/synthesis/HIDDEN_LAYER.v
contains the signal with the correct width.The only way I found to bypass this is to add the following to the
config.tcl
:But this is not the way to go. So what is the problem with the above case? Am I missing something?
Thanks S
Expected Behavior
Synthesis pass
Environment report
Reproduction material
n/a
Relevant log output