Defer compilation of AST of verilog files read in by Yosys till all the files are read

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

https://openlane.readthedocs.io/

Apache License 2.0

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Defer compilation of AST of verilog files read in by Yosys till all the files are read #2100

Closed kareefardi closed 3 months ago

kareefardi commented 3 months ago

Add -defer to read_verilog and run hierarchy -check -top $vtop after all the Verilog files are read

Fixes #2094