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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
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Fix Clock Port Check #2109

Closed donn closed 2 months ago

donn commented 2 months ago

~ Clock port check at beginning of flow now allows bits of a bus to be used as clocks ~ Clock port check at beginning of flow no longer allows outputs to be used as clock ports

dlmiles commented 2 months ago

A read of the patch looks good to me, can't break it trying to run it as: python3.9 scripts/check_clock_ports.py --netlist-in modified.json --top tt_um_module_name "ui_in[0]" "clk" "clk[0]" if that helps

LGTM