Clock Network Delay is 0.0 in timing reports after CTS

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

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Clock Network Delay is 0.0 in timing reports after CTS #2120

Open Jaswanth-Pappula opened 2 months ago

Jaswanth-Pappula commented 2 months ago

Clock Network Delay is showing as 0.00 in timing reports of Max and Min after CTS step even though CTS routing is completed.

You can find it in the image attached below.

Can someone help me in resolving this issue.

maliberty commented 2 months ago

Most likely you need set_propagated_clock [all_clocks]

Jaswanth-Pappula commented 2 months ago

Most likely you need set_propagated_clock [all_clocks]

set_propagated_clock [get_clocks {Clk}] is generated in the cts.sdc file inside results section of the design but nor replicated in the min, max or nominal timing reports and it is just showing ideal.

so, is there any other way to do it instead of using set_propagated_clock [all_clocks].