Generating the PDN fails at the "Hierarchical chip design (with macros)" tutorial

[kietuan]

Description

I’m currently working through the ‘Hierarchical chip design (with macros)’ tutorial, executing the command "./flow.tcl -design regfile_2r1w -tag full_guide_broken_aspect_ratio -overwrite" and have encountered an error at the ‘Chip level integration’ stage, specifically at STEP 9. The process of generating the PDN fails, as indicated by the following error messages:

[ERROR]: while executing the openroad script /openlane/scripts/openroad/pdn.tcl [ERROR]: Log file: designs/regfile_2r1w/runs/full_guide_broken_aspect_ratio/logs/floorplan/9-pdn.log [ERROR]: Last 10 lines of the log file...

The log file 9-pdn.log contains the following relevant information:

[ERROR PDN-0233] Failed to generate full power grid.

Expected Behavior

The flow should run normally as I keep following the tutorial strictly.

Environment report

open_pdks cd1748bb197f9b7af62a54507de6624e30363943
WARNING: issue-survey appears to be running inside the OpenLane
container.

This makes it difficult to rule out issues with your
environment.

Unless instructed specifically to do so, please run this command
outside the OpenLane container.
---

Kernel: Linux v5.15.133.1-microsoft-standard-WSL2
Distribution: centos 7
Python: v3.6.8 (OK)
OpenLane Git Version: 337ffbf4749b8bc6e8d8742ed9a595934142198b
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

337ffbf 2024-04-21T17:01:05+02:00 Update OpenROAD (#2118) - Mohamed Gaber -  (grafted, HEAD -> master, tag: 2024.04.22, origin/master, origin/HEAD)
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane.git (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane.git (push)

Reproduction material

Command to run design: /flow.tcl -design regfile_2r1w -tag full_guide_broken_aspect_ratio -overwrite regfile_2r1w.zip

Relevant log output

OpenROAD da0053d7b0014ab9c87ea148875ff6c2a0f9b658 
Features included (+) or not (-):  +Charts +GPU +GUI +MPL2 +PAR +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Reading ODB at '/openlane/designs/regfile_2r1w/runs/full_guide_broken_aspect_ratio/tmp/floorplan/8-tapcell.odb'…
define_corners Typical
read_liberty -corner Typical /home/tuankiet/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
Using 1e-12 for capacitance...
Using 1e+03 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-09 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/scripts/base.sdc'…
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[INFO]: Setting load to: 0.033442
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[INFO]: Setting timing derate to: 5.0 %
[INFO PDN-0001] Inserting grid: stdcell_grid
[INFO PDN-0001] Inserting grid: macro - lane0
[INFO PDN-0001] Inserting grid: macro - lane1
[WARNING PDN-0232] macro - lane0 does not contain any shapes or vias.
[WARNING PDN-0232] macro - lane1 does not contain any shapes or vias.
[ERROR PDN-0233] Failed to generate full power grid.
PDN-0233