Open fazliemre opened 1 month ago
@fazliemre The issue reproducible is missing some files. Can you share your design configuration file?
@fazliemre The issue reproducible is missing some files. Can you share your design configuration file? set ::env(DESIGN_NAME) "i2c_master_top" set ::env(PDK) "sky130A" set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v] set ::env(CLOCK_PERIOD) 100 set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_NET) "wb_clk_i" set ::env(DESIGN_IS_CORE) 1 set ::env(LEC_ENABLE) 0
set ::env(RUN_LINTER) 1 set ::env(QUIT_ON_LINTER_WARNINGS) 0 set ::env(QUIT_ON_LINTER_ERRORS) 0
set ::env(SYNTH_CLOCK_UNCERTAINTY) 0.25 set ::env(SYNTH_CLOCK_UNCERTAINTY) 0.15
set ::env(SYNTH_STRATEGY) "DELAY 1" set ::env(SYNTH_NO_FLAT) 0 set ::env(SYNTH_SHARE_RESOURCES) 1
set ::env(SYNTH_ADDER_TYPR) "YOSYS" set ::env(BASE_SDC_FILE) [glob $::env(DESIGN_DIR)/src/*.v] set ::env(SYNTH_FLAT_TOP) 0 set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" set ::env(QUIT_ON_TIMING_VIOLATIONS) 1 set ::env(QUIT_ON_SETUP_VIOLATIONS) 1 set ::env(QUIT_ON_HOLD_VIOLATIONS) 1
set ::env(RUN_TAP_DECAP_INSERTION) 1 set ::env(FP_CORE_UTIL) 45 set ::env(FP_ASPECT_RATIO) 1 set ::env(FP_SIZING) "relative" set ::env(FP_PDN_CORE_RING) 1 set ::env(FP_PDN_SKIPTRIM) 0 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(PL_TARGET_DENSITY) 55 set ::env(PL_BASIC_PLACEMENT) 0
set ::env(RUN_CTS) 1 set ::env(RUN_FILL_INSERTION) 1
set ::env(ROUTING_CORES) 4 set ::env(GRT_ALLOW_CONGESTION) 0
set ::env(RUN_CVC) 1
set ::env(BASE_SDC_FILE) [glob $::env(DESIGN_DIR)/src/*.v]
@fazliemre This is not a correct configuration for BASE_SDC_FILE
Description
Hello i have get error, when i run the flow on Openlane in STEP 2.
[ERROR]: during executing sta script /openlane/scripts/openroad/sta/multi_corner.tcl [ERROR]: Log: designs/i2c_master_top/runs/RUN_2024.05.20_19.23.01/logs/synthesis/2-sta.log [ERROR]: Last 10 lines: Using 1e+03 for resistance... Using 1e-09 for time... Using 1e+00 for voltage... Using 1e-03 for current... Using 1e-09 for power... Using 1e-06 for distance... Reading netlist '/openlane/designs/i2c_master_top/runs/RUN_2024.05.20_19.23.01/results/synthesis/i2c_master_top.v'… Reading design constraints file at '/openlane/designs/i2c_master_top/src/i2c_master_bit_ctrl.v /openlane/designs/i2c_master_top/src/i2c_master_defines.v /openlane/designs/i2c_master_top/src/i2c_master_top.v /openlane/designs/i2c_master_top/src/timescale.v /openlane/designs/i2c_master_top/src/i2c_master_byte_ctrl.v'… Error: multi_corner.tcl line 43, cannot open '/openlane/designs/i2c_master_top/src/i2c_master_bit_ctrl.v /openlane/designs/i2c_master_top/src/i2c_master_defines.v /openlane/designs/i2c_master_top/src/i2c_master_top.v /openlane/designs/i2c_master_top/src/timescale.v /openlane/designs/i2c_master_top/src/i2c_master_byte_ctrl.v'. child process exited abnormally
[ERROR]: Creating issue reproducible...
![Screenshot from 2024-05-20 19-54-03](https://github.com/The-OpenROAD-Project/OpenLane/assets/161514093/9808f4ab-b163-4eb2-90f4-b2d41df9547d)
Expected Behavior
I want to pass the this step
Environment report
Reproduction material
issue_reproducible.zip
Relevant log output