Open Fabbboy opened 1 month ago
@Fabbboy The issue reproducible is missing some files. Since this crash happens early in the flow, can you upload your input files (config, rtl, gds..)? It will also be useful to determine if there is an issue in producing the reproducibles in OpenLane.
This is weird. I just zipped the folder and did not change anything. Sadly I currently have no more access to the project.... This was kinda dumb. I give my best to recover it.
@kareefardi -I'm not able to upload the project because it's too big. How should I provide it to you?-
I'm able to upload the project file but I'm not able to compress the whole logs to less or equal the limit I have.
@Fabbboy I can confirm the issue. I will try compiling the latest yosys and see if the crash persists.
Perfect I'm glad its not my fault
Description
I encountered a segmentation fault in the ABC tool while trying to build a Verilog project within the OpenLane container. Despite attempting to resolve all warnings and even reducing the codebase to its minimal form, the error persists. This issue occurs during the synthesis stage managed by Yosys, specifically when executing ABC for technology mapping.
I'm not sure if I have to report this here or in the Yosys Project
Expected Behavior
The ABC tool shouldn't crash
Environment report
Reproduction material
issue_reproducible.zip
Relevant log output