Errors found by linter

[Thanhdat1301]

Description

I am trying to add a verilog file to OpenLane. I followed the instructions in getting_started. Here I create a code counter file then run the following command ./flow.tcl -design . However it gives the following error. Does anyone have a fix for this?

Proposal

No response

[kareefardi]

Can you upload your design and configuration files?

[kareefardi]

Also please follow the issue template and add the information from

python3 ./env.py issue-survey

[Thanhdat1301]

I tested a simple counter file: // 4-bit counter module in Verilog module counter ( input wire clk, // Clock input input wire rst_n, // Active low reset input output reg [3:0] count // 4-bit counter output );

always @(posedge clk or negedge rst_n) begin if (!rst_n) count <= 4'b0000; // Reset counter to 0 else count <= count + 1; // Increment counter on clock edge end

endmodule I haven't changed anything in this config file, it's generated automatically from the commands I followed in getting_started

DESIGN_NAME "Demo" VERILOG_FILES "dir::src/*.v" CLOCK_PORT "clk" CLOCK_PERIOD 10 FP_PDN_MULTILAYER true