Open dhombios opened 3 years ago
I'll add, VHDL is a lot more popular in Europe and is by far the dominant HDL language there (here :) ), taught both at universities and used in the industry.
This is a patch that adds mixed language support for VHDL using GHDL though the Yosys GHDL module.
I adds these new environment variables, trying to match the style of OpenLane (for better or worse):
There are 2 ways to use this new capability, which you can also mix and match:
VHDL is a more complex language than Verilog. It allows for record types, enumeration types, etc that cannot be represented in Verilog. GHDL handles this by mostly flattening types and ports to simple vectors of wires. The results are pretty useful and intuitive, but make sure you understand what it has done especially with respect to top level ports.
Everything works in practice AFAICS, except for escaping VHDL names for LVS. The reason for this is Netgen produces output in JSON, and the OpenLane/openroad scripts use a 3rd party JSON parser in python that throws an exception on names such as \db.o.a[31] The LVS has already happened, but OpenLane exits with an error... workaround: run with RUN_LVS = 0 until you are done working on the module, then rerun with RUN_LVS = 1 to be sure, and read the logs.
On request. It's pretty simple. This has been run with projects as complex as the J2 SuperH compatible CPU core VHDL.diff.gz .
FYI -- @umarcor @antonblanchard
I believe that @antonblanchard has been using VHDL heavily with OpenLane / OpenROAD for taping out https://github.com/antonblanchard/microwatt
This is great! One thing I've struggled with is how to power macros. Right now I modify the generated verilog with a script:
https://github.com/antonblanchard/microwatt/tree/caravel-mpw5-20220323/caravel
But this was developed over a year ago and perhaps the updates to the PDN code in Openlane and OpenROAD render it unnecessary now.
Having an open source toolchain for synthesizing integrated circuits can be really useful for research projects. However, some industries enforce the use of vhdl, which is not highly supported by open source projects (the only open source project with similar capabilities that supports vhdl is Electric EDA). Adding vhdl support to this project will allow universities and engineering research centers to reduce dependency on commercial tools and, therefore, making research more accessible.
As Openlane is based on Yosis, this could be achievable using the GHDL plugin available for it, which adds support for that language and is also open source. Alternatively, Icarus Verilog provides a vhdl to verilog translator.