search

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
1.32k stars 372 forks source link

Manual macro placement for a module other than top level #884

Closed microSharjeel closed 2 years ago

microSharjeel commented 2 years ago

Prompt

Manual macro placement only works when the module that is black box is in the top level of the rtl design. I have design in which I am supposed to place macro for SRAM and that SRAM is deep in the design and not in the top level. OpenLane gives an error (Macro not found when the black box to be place is not in the top level). Is there any solution for this or if this can be enhanced in OpenLane

Proposal

Macro placement can be done for all modules at all levels in RTL design

vijayank88 commented 2 years ago

@microSharjeel
Please provide issue_survey and reproducible tar file

armleo commented 2 years ago

Had the same issue. Was caused by misconfiguration and Verilog RTL issue.

microSharjeel commented 2 years ago

@armleo if you solved it ? if so then can you help ?

armleo commented 2 years ago

My issue was that the sram was not recognized as blackbox. Check synthesis verilog, it should have the balckbox cell.

Check the name too. I made an mistake where the name was incorrect. Check the floorplan def + synthesis netlist for that one.

Also idk, how to properly escape the name. This might be most likely cause.

microSharjeel commented 2 years ago

@armleo Also idk, how to properly escape the name. This might be most likely cause.> ? can not understand I want to place Macro from openRAM. I am using the .lef and .gds files from OpenRAM and the name that I use for blackbox is the same name that is there in the .LEF file

microSharjeel commented 2 years ago

@armleo Have you placed macro in your design at a level other than top level ? If this is the exact scenario then I would like to know about your config.tcl file if you can share that

armleo commented 2 years ago

Unfortunately I cant share it.

The most likely cause is that the name of macro does not exactly match the name in sybthesised netlist. If the synthesis netlist has hierarchy, then the name of the cell has to be escaped according to hierarchy.

Just screenshot and send synthesis netlist with section of macro visible.

microSharjeel commented 2 years ago

Screenshot from 2022-01-26 21-33-18

microSharjeel commented 2 years ago

The name of the macro is in highlight sram_32_128_sky130A

microSharjeel commented 2 years ago

I have used the hierarchical name from the synthesized netlist. I want to write this for anyone who wants to place macro in RTL design at a level other than top level. In this case the hierarchical name of the macro should be used. This issue is now resolved and i will close it @armleo Thanks a lot for help