Unable to Run CHISEL Generated RTL through OpenROAD Flow Scripts

[dalyles]

Subject

[Documentation] for documentation errors.

Describe the bug

Hello,

I'm trying to run a simple full_adder circuit generated by CHISEL and it seems like the flow cannot even get past synthesis. Any help or guidance would be greatly appreciated.

Expected Behavior

The run should be able to successfully process the RTL and go through all the processes in OpenROAD.

Environment

11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
12. Executing OPT pass (performing simple optimizations).
12.1. Executing OPT_EXPR pass (perform const folding).
12.2. Executing OPT_MERGE pass (detect identical cells).
12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
12.5. Executing OPT_MERGE pass (detect identical cells).
12.6. Executing OPT_DFF pass (perform DFF optimizations).
12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
12.8. Executing OPT_EXPR pass (perform const folding).
12.9. Finished OPT passes. (There is nothing left to do.)
Using ABC area script.
[FLOW] Set ABC_CLOCK_PERIOD_IN_PS to: 470000
13. Executing ABC pass (technology mapping using ABC).
13.1. Extracting gate netlist of module `\full_adder' to `<abc-temp-dir>/input.blif'..
13.1.1. Executing ABC.
13.1.2. Re-integrating ABC results.
14. Executing SETUNDEF pass (replace undef values with defined constants).
15. Executing SPLITNETS pass (splitting up multi-bit signals).
16. Executing OPT_CLEAN pass (remove unused cells and wires).
17. Executing HILOMAP pass (mapping to constant drivers).
18. Executing INSBUF pass (insert buffer cells for connected wires).
19. Executing CHECK pass (checking for obvious problems).
20. Printing statistics.
21. Executing Verilog backend.
Warnings: 8 unique messages, 72 total
End of script. Logfile hash: 8cb3fa19b9, CPU: user 0.59s system 0.00s, MEM: 32.18 MB peak
Yosys 0.13+15 (git sha1 bc027b2ca, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os)
Time spent: 25% 2x abc (0 sec), 11% 2x stat (0 sec), ...
Elapsed time: 0:00.77[h:]min:sec. CPU time: user 0.75 sys 0.02 (100%). Peak memory: 33344KB.
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
cp results/nangate45/full_adder/base/1_1_yosys.v results/nangate45/full_adder/base/1_synth.v
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
cp designs/nangate45/full_adder/constraint.sdc results/nangate45/full_adder/base/1_synth.sdc
(/usr/bin/time -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' /home/dlyles/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad -exit -no_init  ./scripts/floorplan.tcl -metrics ./logs/nangate45/full_adder/base/2_1_floorplan.json) 2>&1 | tee ./logs/nangate45/full_adder/base/2_1_floorplan.log
OpenROAD v2.0-8118-gb95ce9901
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
[INFO ODB-0223]     Created 22 technology layers
[INFO ODB-0224]     Created 27 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
[INFO ODB-0222] Reading LEF file: ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225]     Created 135 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
[ERROR STA-0190] full_adder  is not a verilog module.
Error: floorplan.tcl, 3 STA-0190
Command exited with non-zero status 1
Elapsed time: 0:00.23[h:]min:sec. CPU time: user 0.20 sys 0.03 (100%). Peak memory: 90984KB.
make: *** [Makefile:442: results/nangate45/full_adder/base/2_1_floorplan.odb] Error 1

To Reproduce

In order to reproduce this output, You will need the full_adder.v file which is located here: ~/OpenROAD-flow-scripts/flow/designs/src/full_adder

module full_adder(
  input         clock,
  input         reset,
  input         io_in_en,
  input  [31:0] io_in_a,
  input  [31:0] io_in_b,
  input         io_in_c,
  output [31:0] io_out_s,
  output        io_out_c
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [32:0] result; // @[Arithmetic.scala 297:25]
  wire [32:0] _result_T = io_in_a + io_in_b; // @[Arithmetic.scala 299:25]
  wire [32:0] _GEN_1 = {{32'd0}, io_in_c}; // @[Arithmetic.scala 299:36]
  wire [33:0] _result_T_1 = _result_T + _GEN_1; // @[Arithmetic.scala 299:36]
  wire [33:0] _GEN_0 = io_in_en ? _result_T_1 : {{1'd0}, result}; // @[Arithmetic.scala 298:20 299:14 297:25]
  wire [33:0] _GEN_2 = reset ? 34'h0 : _GEN_0; // @[Arithmetic.scala 297:{25,25}]
  assign io_out_s = result[31:0]; // @[Arithmetic.scala 301:23]
  assign io_out_c = result[32]; // @[Arithmetic.scala 302:23]
  always @(posedge clock) begin
    result <= _GEN_2[32:0]; // @[Arithmetic.scala 297:{25,25}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  result = _RAND_0[32:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule

And the config.mk and constraint.sdc at ~/OpenROAD-flow-scripts/flow/designs/nangate45/full_adder

export PLATFORM               = nangate45

export DESIGN_NAME            = full_adder
export DESIGN_NICKNAME        = full_adder

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export ABC_AREA               = 1

export CORE_UTILIZATION       = 40
export CORE_ASPECT_RATIO      = 1
export CORE_MARGIN            = 2
export PLACE_DENSITY         = 0.65

set clk_name  clk
set clk_port_name clock
set clk_period 470
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

And before running the command make in ~/OpenROAD-flow-scripts/flow, you modifiy the makefile by addeing DESIGN_CONFIG=./designs/nangate45/full_adder/config.mk

Relevant log output

No response

Screenshots

No response

Additional Context

No response

[mi-and-core]

your full_adder.v is not a valid verilog file. Add an endmodule.

[dalyles]

your full_adder.v is not a valid verilog file. Add an endmodule.

Hi @mi-and-core good eye. That was a mistake on my part when it came to copying pasting the RTL file, the actual RTL actually has endmodule. I'll update the post.

Thanks

[mi-and-core]

With the mentioned change, not quite old openroad-flowscripts work as expected :

make clean_all make make gui_final

BTW: The clock period (set clk_period 470) in your constraint.sdc looks a bit strange with respect to nangate45. (Unlike in asap7, where the clock period is measured in ps, for nangate45 the period must be specified in ns -i.e. set clk_period 4 )

--close

[dalyles]

After chanign the clock period to 50ns, I get this result below:

Warnings: 8 unique messages, 72 total
End of script. Logfile hash: 8cb3fa19b9, CPU: user 0.56s system 0.01s, MEM: 32.64 MB peak
Yosys 0.13+15 (git sha1 bc027b2ca, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os)
Time spent: 26% 2x abc (0 sec), 11% 2x read_liberty (0 sec), ...
Elapsed time: 0:00.76[h:]min:sec. CPU time: user 0.72 sys 0.03 (100%). Peak memory: 33780KB.
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
cp results/nangate45/full_adder/base/1_1_yosys.v results/nangate45/full_adder/base/1_synth.v
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
cp designs/nangate45/full_adder/constraint.sdc results/nangate45/full_adder/base/1_synth.sdc
(/usr/bin/time -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' /home/dlyles/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad -exit -no_init  ./scripts/floorplan.tcl -metrics ./logs/nangate45/full_adder/base/2_1_floorplan.json) 2>&1 | tee ./logs/nangate45/full_adder/base/2_1_floorplan.log
OpenROAD v2.0-8118-gb95ce9901 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
[INFO ODB-0223]     Created 22 technology layers
[INFO ODB-0224]     Created 27 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
[INFO ODB-0222] Reading LEF file: ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225]     Created 135 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
[ERROR STA-0190] full_adder  is not a verilog module.
Error: floorplan.tcl, 3 STA-0190
Command exited with non-zero status 1
Elapsed time: 0:00.21[h:]min:sec. CPU time: user 0.19 sys 0.02 (99%). Peak memory: 91240KB.
make: *** [Makefile:442: results/nangate45/full_adder/base/2_1_floorplan.odb] Error 1

I'm not sure as to why is says that [ERROR STA-0190] full_adder is not a verilog module.

[dalyles]

@vijayank88 @vvbandeira,

Do you have a moment to look at this?

[dalyles]

Also just to add some context,

I was told that is some relation to the TinyRocket folder and how that plays a role in this process. Any guidance on that would be great and helpful.

Thanks

[dalyles]

With the mentioned change, not quite old openroad-flowscripts work as expected :

@mi-and-core can you please elaborate on what you mean by this?

[mi-and-core]

@dalyles Add endmodule and 'make clean_all' before 'make'

With these changes i can't reproduce the problem. What does 'openroad -version' says ?

Try another simple plain verilog design (e.g. gcd/nangate45 ) in your environment

[mi-and-core]

@dalyles This is the 'final' gds of your verilog generated with Yosys 0.13+15 and openroad v2.0-9070 :

[vijayank88]

@dalyles Please add environment setup:

cd tools/OpenROAD
./etc/Env.sh

Copy & past entire logs what it prints

[vijayank88]

Seems you're using older ORFS commits. Update to latest commit and try again. Instructions here for the update: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/docs/user/FAQS.md#how-do-i-update-openroad-flow-scripts

[vijayank88]

@dalyles I have tested your full_adder.v file locally with your given constraints. Working fine at my end. Recently yosys version got updated. So update your ORFS commit or install freshly and try again.

make DESIGN_CONFIG=./designs/nangate45/full_adder/config.mk clean_all
make DESIGN_CONFIG=./designs/nangate45/full_adder/config.mk

[dalyles]

Quick update,

I followed everyones instruction and did a fresh install of OPFS. For some reason it's still failing on my end. Here is what got dumped onto the console.

[INFO][FLOW] Using platform directory ./platforms/nangate45
./util/markDontUse.py -p "TAPCELL_X1 FILLCELL_X1 AOI211_X1 OAI211_X1" -i platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib -o objects/nangate45/full_adder/base/lib/NangateOpenCellLibrary_typical.lib
Opening file for replace: platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib
Marked 4 cells as dont_use
Commented 0 lines containing "original_pin"
Replaced malformed functions 0
Writing replaced file: objects/nangate45/full_adder/base/lib/NangateOpenCellLibrary_typical.lib
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
(/usr/bin/time -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' /home/dlyles/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys -v 3 -c ./scripts/synth.tcl) 2>&1 | tee ./logs/nangate45/full_adder/base/1_1_yosys.log
1. Executing Verilog-2005 frontend: ./designs/src/full_adder/full_adder.v
2. Executing Liberty frontend.
3. Executing Verilog-2005 frontend: ./platforms/nangate45/cells_clkgate.v
4. Executing SYNTH pass.
4.1. Executing HIERARCHY pass (managing design hierarchy).
4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\full_adder'.
4.2.1. Analyzing design hierarchy..
4.2.2. Analyzing design hierarchy..
4.3. Executing PROC pass (convert processes to netlists).
4.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
4.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
4.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
4.3.4. Executing PROC_INIT pass (extract init attributes).
4.3.5. Executing PROC_ARST pass (detect async resets in processes).
4.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
4.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).
4.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
4.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
4.3.11. Executing OPT_EXPR pass (perform const folding).
4.4. Executing FLATTEN pass (flatten design).
4.5. Executing OPT_EXPR pass (perform const folding).
4.6. Executing OPT_CLEAN pass (remove unused cells and wires).
4.7. Executing CHECK pass (checking for obvious problems).
4.8. Executing OPT pass (performing simple optimizations).
4.8.1. Executing OPT_EXPR pass (perform const folding).
4.8.2. Executing OPT_MERGE pass (detect identical cells).
4.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
4.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
4.8.5. Executing OPT_MERGE pass (detect identical cells).
4.8.6. Executing OPT_DFF pass (perform DFF optimizations).
4.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
4.8.8. Executing OPT_EXPR pass (perform const folding).
4.8.9. Finished OPT passes. (There is nothing left to do.)
4.9. Executing FSM pass (extract and optimize FSM).
4.9.1. Executing FSM_DETECT pass (finding FSMs in design).
4.9.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.9.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.9.4. Executing OPT_CLEAN pass (remove unused cells and wires).
4.9.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.9.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.9.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.9.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.10. Executing OPT pass (performing simple optimizations).
4.10.1. Executing OPT_EXPR pass (perform const folding).
4.10.2. Executing OPT_MERGE pass (detect identical cells).
4.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
4.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
4.10.5. Executing OPT_MERGE pass (detect identical cells).
4.10.6. Executing OPT_DFF pass (perform DFF optimizations).
4.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
4.10.8. Executing OPT_EXPR pass (perform const folding).
4.10.9. Rerunning OPT passes. (Maybe there is more to do..)
4.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
4.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
4.10.12. Executing OPT_MERGE pass (detect identical cells).
4.10.13. Executing OPT_DFF pass (perform DFF optimizations).
4.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
4.10.15. Executing OPT_EXPR pass (perform const folding).
4.10.16. Finished OPT passes. (There is nothing left to do.)
4.11. Executing WREDUCE pass (reducing word size of cells).
4.12. Executing PEEPOPT pass (run peephole optimizers).
4.13. Executing OPT_CLEAN pass (remove unused cells and wires).
4.14. Executing ALUMACC pass (create $alu and $macc cells).
4.15. Executing SHARE pass (SAT-based resource sharing).
4.16. Executing OPT pass (performing simple optimizations).
4.16.1. Executing OPT_EXPR pass (perform const folding).
4.16.2. Executing OPT_MERGE pass (detect identical cells).
4.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
4.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
4.16.5. Executing OPT_MERGE pass (detect identical cells).
4.16.6. Executing OPT_DFF pass (perform DFF optimizations).
4.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
4.16.8. Executing OPT_EXPR pass (perform const folding).
4.16.9. Rerunning OPT passes. (Maybe there is more to do..)
4.16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
4.16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
4.16.12. Executing OPT_MERGE pass (detect identical cells).
4.16.13. Executing OPT_DFF pass (perform DFF optimizations).
4.16.14. Executing OPT_CLEAN pass (remove unused cells and wires).
4.16.15. Executing OPT_EXPR pass (perform const folding).
4.16.16. Finished OPT passes. (There is nothing left to do.)
4.17. Executing MEMORY pass.
4.17.1. Executing OPT_MEM pass (optimize memories).
4.17.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
4.17.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
4.17.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
4.17.5. Executing OPT_CLEAN pass (remove unused cells and wires).
4.17.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.17.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
4.17.8. Executing OPT_CLEAN pass (remove unused cells and wires).
4.17.9. Executing MEMORY_COLLECT pass (generating $mem cells).
4.18. Executing OPT_CLEAN pass (remove unused cells and wires).
4.19. Executing OPT pass (performing simple optimizations).
4.19.1. Executing OPT_EXPR pass (perform const folding).
4.19.2. Executing OPT_MERGE pass (detect identical cells).
4.19.3. Executing OPT_DFF pass (perform DFF optimizations).
4.19.4. Executing OPT_CLEAN pass (remove unused cells and wires).
4.19.5. Finished fast OPT passes.
4.20. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
4.21. Executing OPT pass (performing simple optimizations).
4.21.1. Executing OPT_EXPR pass (perform const folding).
4.21.2. Executing OPT_MERGE pass (detect identical cells).
4.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
4.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
4.21.5. Executing OPT_MERGE pass (detect identical cells).
4.21.6. Executing OPT_SHARE pass.
4.21.7. Executing OPT_DFF pass (perform DFF optimizations).
4.21.8. Executing OPT_CLEAN pass (remove unused cells and wires).
4.21.9. Executing OPT_EXPR pass (perform const folding).
4.21.10. Finished OPT passes. (There is nothing left to do.)
4.22. Executing TECHMAP pass (map to technology primitives).
4.22.1. Executing Verilog-2005 frontend: /home/dlyles/OpenROAD-flow-scripts/tools/install/yosys/bin/../share/yosys/techmap.v
4.22.2. Continuing TECHMAP pass.
4.23. Executing OPT pass (performing simple optimizations).
4.23.1. Executing OPT_EXPR pass (perform const folding).
4.23.2. Executing OPT_MERGE pass (detect identical cells).
4.23.3. Executing OPT_DFF pass (perform DFF optimizations).
4.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).
4.23.5. Finished fast OPT passes.
4.24. Executing ABC pass (technology mapping using ABC).
4.24.1. Extracting gate netlist of module `\full_adder' to `<abc-temp-dir>/input.blif'..
4.25. Executing OPT pass (performing simple optimizations).
4.25.1. Executing OPT_EXPR pass (perform const folding).
4.25.2. Executing OPT_MERGE pass (detect identical cells).
4.25.3. Executing OPT_DFF pass (perform DFF optimizations).
4.25.4. Executing OPT_CLEAN pass (remove unused cells and wires).
4.25.5. Finished fast OPT passes.
4.26. Executing HIERARCHY pass (managing design hierarchy).
4.26.1. Analyzing design hierarchy..
4.26.2. Analyzing design hierarchy..
4.27. Printing statistics.
4.28. Executing CHECK pass (checking for obvious problems).
5. Executing OPT pass (performing simple optimizations).
5.1. Executing OPT_EXPR pass (perform const folding).
5.2. Executing OPT_MERGE pass (detect identical cells).
5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
5.5. Executing OPT_MERGE pass (detect identical cells).
5.6. Executing OPT_DFF pass (perform DFF optimizations).
5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
5.8. Executing OPT_EXPR pass (perform const folding).
5.9. Rerunning OPT passes. (Maybe there is more to do..)
5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
5.12. Executing OPT_MERGE pass (detect identical cells).
5.13. Executing OPT_DFF pass (perform DFF optimizations).
5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
5.15. Executing OPT_EXPR pass (perform const folding).
5.16. Finished OPT passes. (There is nothing left to do.)
6. Executing EXTRACT_FA pass (find and extract full/half adders).
7. Executing TECHMAP pass (map to technology primitives).
7.1. Executing Verilog-2005 frontend: ./platforms/nangate45/cells_adders.v
7.2. Continuing TECHMAP pass.
8. Executing TECHMAP pass (map to technology primitives).
8.1. Executing Verilog-2005 frontend: /home/dlyles/OpenROAD-flow-scripts/tools/install/yosys/bin/../share/yosys/techmap.v
8.2. Continuing TECHMAP pass.
9. Executing OPT pass (performing simple optimizations).
9.1. Executing OPT_EXPR pass (perform const folding).
9.2. Executing OPT_MERGE pass (detect identical cells).
9.3. Executing OPT_DFF pass (perform DFF optimizations).
9.4. Executing OPT_CLEAN pass (remove unused cells and wires).
9.5. Finished fast OPT passes.
10. Executing TECHMAP pass (map to technology primitives).
10.1. Executing Verilog-2005 frontend: ./platforms/nangate45/cells_latch.v
10.2. Continuing TECHMAP pass.
11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
12. Executing OPT pass (performing simple optimizations).
12.1. Executing OPT_EXPR pass (perform const folding).
12.2. Executing OPT_MERGE pass (detect identical cells).
12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
12.5. Executing OPT_MERGE pass (detect identical cells).
12.6. Executing OPT_DFF pass (perform DFF optimizations).
12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
12.8. Executing OPT_EXPR pass (perform const folding).
12.9. Finished OPT passes. (There is nothing left to do.)
Using ABC area script.
[FLOW] Set ABC_CLOCK_PERIOD_IN_PS to: 50000
13. Executing ABC pass (technology mapping using ABC).
13.1. Extracting gate netlist of module `\full_adder' to `<abc-temp-dir>/input.blif'..
13.1.1. Executing ABC.
13.1.2. Re-integrating ABC results.
14. Executing SETUNDEF pass (replace undef values with defined constants).
15. Executing SPLITNETS pass (splitting up multi-bit signals).
16. Executing OPT_CLEAN pass (remove unused cells and wires).
17. Executing HILOMAP pass (mapping to constant drivers).
18. Executing INSBUF pass (insert buffer cells for connected wires).
19. Executing CHECK pass (checking for obvious problems).
20. Printing statistics.
21. Executing Verilog backend.
Warnings: 8 unique messages, 72 total
End of script. Logfile hash: 8cb3fa19b9, CPU: user 0.58s system 0.01s, MEM: 32.52 MB peak
Yosys 0.13+15 (git sha1 bc027b2ca, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os)
Time spent: 25% 2x abc (0 sec), 11% 2x stat (0 sec), ...
Elapsed time: 0:00.78[h:]min:sec. CPU time: user 0.74 sys 0.04 (100%). Peak memory: 33676KB.
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
cp results/nangate45/full_adder/base/1_1_yosys.v results/nangate45/full_adder/base/1_synth.v
mkdir -p ./results/nangate45/full_adder/base ./logs/nangate45/full_adder/base ./reports/nangate45/full_adder/base
cp designs/nangate45/full_adder/constraint.sdc results/nangate45/full_adder/base/1_synth.sdc
(/usr/bin/time -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' /home/dlyles/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad -exit -no_init  ./scripts/floorplan.tcl -metrics ./logs/nangate45/full_adder/base/2_1_floorplan.json) 2>&1 | tee ./logs/nangate45/full_adder/base/2_1_floorplan.log
OpenROAD v2.0-9070-gbb341ffb9 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
[INFO ODB-0223]     Created 22 technology layers
[INFO ODB-0224]     Created 27 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
[INFO ODB-0222] Reading LEF file: ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225]     Created 135 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
[ERROR STA-0190] full_adder  is not a verilog module.
Error: floorplan.tcl, 3 STA-0190
Command exited with non-zero status 1
Elapsed time: 0:00.22[h:]min:sec. CPU time: user 0.21 sys 0.01 (100%). Peak memory: 91328KB.
make: *** [Makefile:457: results/nangate45/full_adder/base/2_1_floorplan.odb] Error 1

[maliberty]

I don't have any problem running this either. What do you have in results/nangate45/full_adder/base/1_1_yosys.v? Mine starts:

/* Generated by Yosys 0.13+15 (git sha1 bc027b2ca, gcc 8.3.1 -fPIC -Os) */

module full_adder(clock, reset, io_in_en, io_in_a, io_in_b, io_in_c, io_out_s, io_out_c);

[dalyles]

This is what I have on my end:

/* Generated by Yosys 0.13+15 (git sha1 bc027b2ca, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os) */

module full_adder(clock, reset, io_in_en, io_in_a, io_in_b, io_in_c, io_out_s, io_out_c);

[maliberty]

I don't see how you get "full_adder is not a verilog module." when you have it in your Verilog. Something odd is happening at your side that I can't explain. Can you tar up your workspace for investigation?

[dalyles]

Which part of the workspace is good for doing this? I tried to tar up my current repo and it's about 3.52 GB and that is too large to upload here.

Thanks

[dalyles]

@maliberty I made a google drive link.

https://drive.google.com/file/d/1dOsR0v7ycP4Y77LHABrXfxjq2zrPAlos/view?usp=sharing This should work, it's a large file so beware.

Thanks!

[mi-and-core]

I can confirm the problem.

There is an error in your config.mk. Delete the extra space at the end of line 3 So instead of

'export DESIGN_NAME = full_adder ' 'export DESIGN_NAME = full_adder'

(otherwise module isn't set in STAs VerilogReader():1749) That solves the problem on my side.

[maliberty]

In your config.mk you have

export DESIGN_NAME            = full_adder 

there is an extraneous space character after 'full_adder' (ie 'full_adder ') that is confusing the flow.

[dalyles]

Thanks so much for your help everybody. I also removed the whitespace and I have it working on my end.