Closed oharboe closed 8 months ago
Thanks much for your help with validation. Current support for insertion delay is done as follows:
This approach did improve clock skew for one of the unit tests (src/cts/test/array_ins_delay.tcl). from 0.25 to 0.16. But this is not making any difference for the mock-array testcase. Let us get back to you on how we can improve the insertion delay handling.
Thanks.
This issue is a duplicate of https://github.com/The-OpenROAD-Project/OpenROAD/issues/3759 which has been resolved.
Description
@tspyrou @precisionmoon @maliberty
unzip insertion-delay.zip
In the output, we can see that the insertion delay has been detected:
Now load the generated output:
The element clock network delay does not appear to have been taken into account in the CTS. The flip flops have the shortest insertion delay and the elements the longest, whereas I expected the the oposite.
Suggested Solution
Modify CTS so that elements have the shortest network insertion delay and the flip flops the shortest
Additional Context
No response