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The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
https://theopenroadproject.org/
BSD 3-Clause "New" or "Revised" License
1.54k stars 540 forks source link

OpenROAD is crashing while starting FastRoute #159

Closed tamimcse closed 4 years ago

tamimcse commented 4 years ago

OpenROAD is crashing while starting FastRoute for https://github.com/tamimcse/test/blob/master/top.v. The Verilog is generated using Bambu HLS. The OpenROAD script is https://github.com/tamimcse/test/blob/master/bash_script.sh. The output is as following: You will see the crash at the very end.

.....
......
yosys> opt_clean -purge

Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy..
Removed 96 unused cells and 9494 unused wires.
<suppressed ~183 debug messages>
y_typical.lib iberty /opt/panda/share/panda//nangate45/lib/NangateOpenCellLibrary

Printing statistics.
=== _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ===

Number of wires: 20066
Number of wire bits: 21196
Number of public wires: 2469
Number of public wire bits: 3599
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 18580
AND2_X1 1925
AND2_X2 49
AND2_X4 45
AND3_X1 488
AND3_X2 3
AND3_X4 6
AND4_X1 120
AND4_X2 3
AND4_X4 3
AOI211_X1 272
AOI211_X2 3
AOI21_X1 882
AOI21_X2 3
AOI221_X1 1
AOI221_X2 2
AOI221_X4 33
AOI22_X1 22
BUF_X1 4070
BUF_X16 2
BUF_X2 115
BUF_X4 273
BUF_X8 5
CLKBUF_X2 58
CLKBUF_X3 3
DFF_X1 1514
INV_X1 807
INV_X2 18
INV_X32 5
INV_X4 6
LOGIC0_X1 1
MUX2_X1 1143
MUX2_X2 4
NAND2_X1 1288
NAND2_X2 3
NAND2_X4 1
NAND3_X1 451
NAND3_X2 1
NAND4_X1 84
NAND4_X2 1
NOR2_X1 1262
NOR2_X2 11
NOR2_X4 9
NOR3_X1 335
NOR3_X2 1
NOR3_X4 1
NOR4_X1 58
NOR4_X2 2
NOR4_X4 2
OAI211_X1 356
OAI211_X2 3
OAI21_X1 615
OAI21_X2 1
OAI221_X1 44
OAI22_X1 30
OAI22_X2 1
OR2_X1 228
OR2_X2 5
OR2_X4 2
OR3_X1 236
OR4_X1 111
OR4_X2 1
XNOR2_X1 668
XOR2_X1 873
XOR2_X2 12

Chip area for module '_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy': 25630.164000

S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy_mapped.vPhPtS_PjS_S1_S_S1_S_S1
21. Executing Verilog backend.
Dumping module `_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy'.

yosys> exit

Warnings: 8 unique messages, 72 total
End of script. Logfile hash: 9dd2f6b66b, CPU: user 35.81s system 0.18s, MEM: 104.99 MB peak
Yosys 0.9+1706 (git sha1 b7419544, gcc 7.4.0-1ubuntu1~18.04.1 -fPIC -Os)
Time spent: 28% 30x opt_clean (9 sec), 17% 25x opt_merge (6 sec), ...
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged.lef
Startpoint: 34756 (rising edge-triggered flip-flop clocked by clock)
Endpoint: 36070 (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

Delay Time Description
0.00 0.00 clock clock (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ 34756/CK (DFF_X1)
0.08 0.08 ^ 34756/Q (DFF_X1)
0.17 0.26 ^ 30643/Z (BUF_X1)
0.02 0.28 v 17612/ZN (NOR2_X4)
0.05 0.33 v 17614/ZN (AND2_X4)
0.03 0.36 ^ 17703/ZN (NOR2_X2)
0.02 0.38 v 17719/ZN (INV_X1)
0.05 0.43 ^ 17720/ZN (AOI221_X2)
0.04 0.47 ^ 17721/ZN (AND2_X2)
0.03 0.50 ^ 17727/ZN (AND2_X4)
0.03 0.53 ^ 17749/ZN (AND2_X4)
0.03 0.56 ^ 17750/Z (BUF_X4)
0.04 0.59 ^ 21064/ZN (AND3_X4)
0.04 0.64 ^ 21069/ZN (AND3_X2)
0.04 0.67 ^ 21345/ZN (AND2_X4)
0.03 0.70 ^ 21451/Z (BUF_X8)
0.06 0.76 v 21452/Z (MUX2_X1)
0.03 0.79 v 21453/ZN (AND2_X1)
0.06 0.85 ^ 21456/ZN (AOI211_X2)
0.01 0.86 v 21467/ZN (NOR3_X1)
0.04 0.90 v 21487/ZN (OR2_X1)
0.06 0.96 v 21488/Z (MUX2_X1)
0.03 0.98 v 32559/Z (BUF_X1)
0.00 0.98 v 36070/D (DFF_X1)
0.98 data arrival time

1.00 1.00 clock clock (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ 36070/CK (DFF_X1)
-0.04 0.96 library setup time
0.96 data required time
0.96 data required time
-0.98 data arrival time
-0.02 slack (VIOLATED)
Design area 102521 u^2 100% utilization.
Info: Added 428 rows of 3158 sites.
WARNING: force pin spread option has no effect when using random pin placement

Running IO placement

Num of slots 7698
Num of I/O 1173
Num of I/O w/sink 1130
Num of I/O w/o sink 43
Slots Per Section 200
Slots Increase Factor 0.01
Usage Per Section 0.8
Usage Increase Factor 0.01
Force Pin Spread 1
WARNING: running random pin placement
RandomMode Even

IO placement done.
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef
Notice 0:
Reading DEF file: OpenROAD_results/2_2_floorplan_io.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: Created 1173 pins.
Notice 0: Created 18580 components and 95604 component-terminals.
Notice 0: Created 21186 nets and 58444 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_2_floorplan_io.def
invalid command name "STEP 3: Timing Driven Mixed Sized Placement"
No macros found: Skipping global_placement
fixIoPins.py : Fixing Pins in Def file
Replacements made - West:337 South:249 East:338 North:249
fixIoPins.py : Finished
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef
Notice 0:
Reading DEF file: OpenROAD_results/2_3_floorplan_tdms.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: Created 1173 pins.
Notice 0: Created 18580 components and 95604 component-terminals.
Notice 0: Created 21186 nets and 58444 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_3_floorplan_tdms.def
No macros found: Skipping macro_placement
##Power Delivery Network Generator: Generating PDN

config: /opt/panda/share/panda//nangate45/pdn.cfg
Design Name is _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Reading BEOL LEF and gathering information ...
****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: metal1 - Width: 0.170 Pitch: 2.400 Offset: 0.000
Straps
Layer: metal4 - Width: 0.480 Pitch: 56.000 Offset: 2.000
Layer: metal7 - Width: 1.400 Pitch: 40.000 Offset: 2.000
Connect: {metal1 metal4} {metal4 metal7}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY
Straps
Layer: metal5 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Connect: {metal4_PIN_ver metal5} {metal5 metal6} {metal6 metal7}
Type: macro, macro_2
Macro orientation: R90 R270 MXR90 MYR90
Straps
Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Connect: {metal4_PIN_hor metal6} {metal6 metal7}
**** END INFO ****
Inserting stdcell grid - grid
Writing to database
Running tapcell...
Step 1: Cut rows...
---- Macro blocks found: 0
---- #Original rows: 428
---- #Cut rows: 0
Step 2: Insert endcaps...
---- #Endcaps inserted: 856
Step 3: Insert tapcells...
---- #Tapcells inserted: 860
Running tapcell... Done!
[INFO] TargetDensity = 0.700000
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
[PROC] Begin Filling Replace Structure ...
[INFO] DEF DBU = 2000
[INFO] RowHeight = 2800.000000
[INFO] ScaleDownUnit = 311.111115
[INFO] CoreAreaLxLy = (20140.000000, 22400.000000)
[INFO] CoreAreaUxUy = (1220180.000000, 1220800.000000)
[INFO] OffsetCoordi = (2260.000000, 0.000000)
[INFO] ScaleDownRowHeight = 9.000000
[INFO] Modules = 18580
[INFO] Terminals = 2889
[PROC] Begin Generate Nets ...
[INFO] NumNets = 21186
[INFO] NumPins = 59617
[PROC] End Generate Nets
[INFO] Inserted Dummy Terms = 0
[PROC] Begin Generate Rows ...
[INFO] RowSize = (1.221429, 9.000000)
[INFO] NumRows = 428
[PROC] End Generate Rows
[INFO] AspectRatio = 0.998633
[INFO] RowMinXY = (72.000000, 79.264282)
[INFO] RowMaxXY = (3929.271240, 3931.264160)
[INFO] NumPlaceStdCells = 18580
[INFO] NumPlaceMacros = 0
[INFO] RowSize = (1.221429, 9.000000)
[INFO] NumRows = 428
[INFO] GlobalAreaLxLy = (7.489285, 7.489285)
[INFO] GlobalAreaUxUy = (3993.717773, 3996.610596)
[INFO] PlaceAreaLxLy = (72.000000, 79.264160)
[INFO] PlaceAreaUxUy = (3929.271240, 3931.264160)
[PROC] End Filling Replace Structure
PROC: Conjugate Gradient (CG) method to obtain the IP
INFO: The Initial HPWL is 524644.543317
INFO: The Matrix Size is 18580
INFO: IP 0, CG Error 0.000027, HPWL 545957.517281, CPUtime 0.17
INFO: IP 1, CG Error 0.000006, HPWL 526126.977911, CPUtime 0.21
INFO: IP 2, CG Error 0.000001, HPWL 523085.066241, CPUtime 0.22
INFO: IP 3, CG Error 0.000001, HPWL 522274.195831, CPUtime 0.21
INFO: IP 4, CG Error 0.000001, HPWL 521964.732325, CPUtime 0.19
INFO: IP 5, CG Error 0.000000, HPWL 521564.830225, CPUtime 0.21
===HPWL(MICRON)====================================
Mode : Initial Placement
HPWL : 735601.8216
x= 369036.8821 y= 366564.9395
[INFO] TotalPlaceArea = 14858209.000000
[INFO] TotalFixedArea = 18862.050781
[INFO] TotalWhiteSpaceArea = 14839347.000000
[INFO] TotalPlaceMacrosArea = 0.000000
[INFO] TotalPlaceStdCellsArea = 2692896.250000
[INFO] Util(%) = 18.123962
[INFO] 80pCellArea = 139.526581
[INFO] FillerInit: TotalFillerArea = 7694647.000000
[INFO] FillerInit: NumFillerCells = 55146
[INFO] FillerInit: FillerCellArea = 139.533539
[INFO] FillerInit: FillerCellSize = (15.503726, 9.000000)
[INFO] FillerInit: NumCells = 73726
[INFO] FillerInit: NumModules = 18580
[INFO] FillerInit: NumFillers = 55146
INFO: D_MSH = 1024
INFO: MSH(X, Y) = (32, 32)
INFO: dim_bin_cGP2D.(x,y) = (256, 256)
cell Init 2D:
tier->bin_stp: (15.0675 15.0469)
tier->half_bin_stp: (7.5337 7.5234)
PROC: Start NESTEROV's Optimization
PROC: Global Lagrangian Multiplier is Applied
[INFO] Timing: WNS = 1.29948e-11
[INFO] Timing: TNS = 0
[INFO] Nesterov: 0 OverFlow: 0.9854 ScaledHpwl: 3353720.0000
[INFO] Timing: WNS = -9.08862e-12
[INFO] Timing: TNS = -1.37044e-11
[INFO] Nesterov: 10 OverFlow: 0.7612 ScaledHpwl: 4656717.5000
[INFO] Nesterov: 20 OverFlow: 0.7271 ScaledHpwl: 4600205.0000
[INFO] Nesterov: 30 OverFlow: 0.7259 ScaledHpwl: 4532463.0000
[INFO] Nesterov: 40 OverFlow: 0.7285 ScaledHpwl: 4490022.5000
[INFO] Nesterov: 50 OverFlow: 0.7235 ScaledHpwl: 4512176.5000
[INFO] Nesterov: 60 OverFlow: 0.7214 ScaledHpwl: 4498370.5000
[INFO] Nesterov: 70 OverFlow: 0.7225 ScaledHpwl: 4486582.0000
[INFO] Nesterov: 80 OverFlow: 0.7223 ScaledHpwl: 4493103.0000
[INFO] Nesterov: 90 OverFlow: 0.7214 ScaledHpwl: 4493090.0000
[INFO] Nesterov: 100 OverFlow: 0.7219 ScaledHpwl: 4488126.0000
[INFO] Nesterov: 110 OverFlow: 0.7223 ScaledHpwl: 4489798.5000
[INFO] Nesterov: 120 OverFlow: 0.7219 ScaledHpwl: 4492216.0000
[INFO] Nesterov: 130 OverFlow: 0.7219 ScaledHpwl: 4491156.5000
[INFO] Nesterov: 140 OverFlow: 0.7219 ScaledHpwl: 4491949.0000
[INFO] Nesterov: 150 OverFlow: 0.7213 ScaledHpwl: 4494138.0000
[INFO] Nesterov: 160 OverFlow: 0.7207 ScaledHpwl: 4495404.0000
[INFO] Nesterov: 170 OverFlow: 0.7195 ScaledHpwl: 4498037.5000
[INFO] Nesterov: 180 OverFlow: 0.7177 ScaledHpwl: 4502708.0000
[INFO] Nesterov: 190 OverFlow: 0.7145 ScaledHpwl: 4507794.5000
[INFO] Nesterov: 200 OverFlow: 0.7106 ScaledHpwl: 4516302.0000
[INFO] Nesterov: 210 OverFlow: 0.7026 ScaledHpwl: 4528353.0000
[INFO] Nesterov: 220 OverFlow: 0.6926 ScaledHpwl: 4537470.5000
[INFO] Nesterov: 230 OverFlow: 0.6770 ScaledHpwl: 4543792.0000
[INFO] Nesterov: 240 OverFlow: 0.6535 ScaledHpwl: 4535685.5000
[INFO] Timing: WNS = -5.55014e-11
[INFO] Timing: TNS = -5.22214e-10
[INFO] Nesterov: 250 OverFlow: 0.6285 ScaledHpwl: 4530373.0000
[INFO] Nesterov: 260 OverFlow: 0.5989 ScaledHpwl: 4576544.0000
[INFO] Nesterov: 270 OverFlow: 0.5632 ScaledHpwl: 4603646.0000
[INFO] Nesterov: 280 OverFlow: 0.5264 ScaledHpwl: 4607634.0000
[INFO] Nesterov: 290 OverFlow: 0.4824 ScaledHpwl: 4654078.0000
[INFO] Timing: WNS = -1.06277e-10
[INFO] Timing: TNS = -2.22512e-09
[INFO] Nesterov: 300 OverFlow: 0.4519 ScaledHpwl: 4672081.0000
[INFO] Nesterov: 310 OverFlow: 0.4206 ScaledHpwl: 4691820.0000
[INFO] Nesterov: 320 OverFlow: 0.3851 ScaledHpwl: 4693493.0000
[INFO] Nesterov: 330 OverFlow: 0.3558 ScaledHpwl: 4698090.0000
[INFO] Nesterov: 340 OverFlow: 0.3219 ScaledHpwl: 4705394.0000
[INFO] Nesterov: 350 OverFlow: 0.2854 ScaledHpwl: 4708784.0000
[INFO] Timing: WNS = -1.50303e-10
[INFO] Timing: TNS = -2.67458e-09
[INFO] Nesterov: 360 OverFlow: 0.2545 ScaledHpwl: 4708413.0000
[INFO] Nesterov: 370 OverFlow: 0.2222 ScaledHpwl: 4707805.5000
[INFO] Timing: WNS = -1.4887e-10
[INFO] Timing: TNS = -2.59766e-09
[INFO] Nesterov: 380 OverFlow: 0.1903 ScaledHpwl: 4707631.5000
[INFO] Nesterov: 390 OverFlow: 0.1622 ScaledHpwl: 4708060.5000
[INFO] Nesterov: 400 OverFlow: 0.1380 ScaledHpwl: 4708762.5000
[INFO] Nesterov: 410 OverFlow: 0.1158 ScaledHpwl: 4712566.5000
[INFO] Nesterov: 420 OverFlow: 0.0998 ScaledHpwl: 4717579.5000
[INFO] Timing: WNS = -1.53279e-10
[INFO] Timing: TNS = -2.60917e-09
HP wire length: 731895
Worst slack: -1.53e-01
Total negative slack: -2.61e+00
Warning: cell 'OAI211_X1}' not found.
Error: get_property is not an object.
Inserted 1091 input buffers.
Inserted 81 output buffers.
Resized 5488 instances.
Inserted 0 hold buffers.
-------------------- Design Stats ------------------------------
core area : (20140, 22400) (1220180, 1220800)
total cells : 21468
multi cells : 0
fixed cells : 1716
nets : 22360
design area : 1438127936000.000
total fixed area : 1825824000.000
total movable area : 284683840000.000
design utilization : 19.821
rows : 428
row height : 2800
Check Legality
row check ==> PASS
site check ==> PASS
power check ==> PASS
edge_check ==> PASS
placed_check ==>> PASS
overlap_check ==> PASS
-------------------- Placement Analysis ------------------------
total displacement : 62095532
average displacement : 2892
max displacement : 66070
original HPWL : 738875.682
legalized HPWL : 752026.493
delta HPWL : 2%
TritonCTS 2.0 *
Current time: Thu Mar 19 22:26:59 2020

Import characterization *
Reading LUT file "/opt/panda/share/panda//nangate45/tritonCTS/lut.txt"
Min. len Max. len Min. cap Max. cap Min. slew Max. slew
2 8 1 52 1 24
[WARNING] 180 wires are pure wire and no slew degration.
TritonCTS forced slew degradation on these wires.
Num wire segments: 4994
Num keys in characterization LUT: 1677
Actual min input cap: 8
Reading solution list file "/opt/panda/share/panda//nangate45/tritonCTS/sol_list.txt"

Find clock roots *
User did not specify clock roots.
Using OpenSTA to find clock roots.
Looking for clock sources...
Clock names: clock

Populate TritonCTS *
Initializing clock nets
Number of user-input clocks: 1 ( "clock" )
Looking for clock nets in the design
Net "clock" found
clock

Check characterization *
The chacterization used 1 buffer(s) types. All of them are in the loaded DB.
Build clock trees *
Generating H-Tree topology for net clock...
Tot. number of sinks: 1514
Wire segment unit: 20000 dbu (10 um)
Original sink region: [(231990, 315170), (972610, 919970)]
Normalized sink region: [(12, 16), (49, 46)]
Width: 37
Height: 30
Level 1
Direction: Horizontal

sinks per sub-region: 757
Sub-region size: 19 X 30
Segment length (rounded): 10
Key: 3192 outSlew: 1 load: 1 length: 8 isBuffered: 1
Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
Level 2
Direction: Vertical

sinks per sub-region: 379
Sub-region size: 19 X 15
Segment length (rounded): 8
Key: 3206 outSlew: 1 load: 1 length: 8 isBuffered: 1
Level 3
Direction: Horizontal

sinks per sub-region: 190
Sub-region size: 9 X 15
Segment length (rounded): 4
Key: 1170 outSlew: 12 load: 1 length: 4 isBuffered: 1
Level 4
Direction: Vertical

sinks per sub-region: 95
Sub-region size: 9 X 8
Segment length (rounded): 4
Key: 1242 outSlew: 12 load: 1 length: 4 isBuffered: 1
Level 5
Direction: Horizontal

sinks per sub-region: 48
Sub-region size: 5 X 8
Segment length (rounded): 2
Key: 548 outSlew: 2 load: 1 length: 2 isBuffered: 1
[WARNING] Creating fake entries in the LUT.
Level 6
Direction: Vertical

sinks per sub-region: 24
Sub-region size: 5 X 4
Segment length (rounded): 1
Key: 5029 outSlew: 12 load: 1 length: 1 isBuffered: 1
Level 7
Direction: Horizontal

sinks per sub-region: 12
Sub-region size: 2 X 4
Segment length (rounded): 1
Key: 5039 outSlew: 12 load: 1 length: 1 isBuffered: 1
Stop criterion found. Max number of sinks is (15)
Building clock sub nets...
Number of sinks covered: 1514
Clock topology of net "clock" done.

Post CTS opt *
Avg. source sink dist: 46402 dbu.
Num outlier sinks: 3

Write data to DB *
Writing clock net "clock" to DB
Created 258 clock buffers.
Created 258 clock nets.

Current time: Thu Mar 19 22:26:59 2020
... End of TritonCTS execution.
-------------------- Design Stats ------------------------------
core area : (20140, 22400) (1220180, 1220800)
total cells : 21726
multi cells : 0
fixed cells : 1716
nets : 22618
design area : 1438127936000.000
total fixed area : 1825824000.000
total movable area : 287720496000.000
design utilization : 20.032
rows : 428
row height : 2800
Check Legality
row check ==> PASS
site check ==> PASS
power check ==> PASS
edge_check ==> PASS
placed_check ==>> PASS
overlap_check ==> PASS
-------------------- Placement Analysis ------------------------
total displacement : 1657681
average displacement : 76
max displacement : 16853
original HPWL : 763228.133
legalized HPWL : 763580.620
delta HPWL : 0%
Adjust layer 2 in 70.0%
Adjust layer 3 in 70.0%
*** buffer overflow detected ***: openroad terminated
eder-matheus commented 4 years ago

Moved to FastRoute repo (https://github.com/The-OpenROAD-Project/FastRoute/issues/19)