The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
https://theopenroadproject.org/
BSD 3-Clause "New" or "Revised" License
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[ERROR DRT-0085] Valid access pattern combination not found for <instance_name> #3754

Closed techstuds closed 9 months ago

techstuds commented 1 year ago

Describe the bug

I'm facing this error at the pin_access step in global routing. The corresponding cells do not overlap with others and have enough space around them for routing. There are many other instances with the same master where everything went well. The design has 15192 unique inst patterns (see routing.log) and for some reason the router is having trouble accessing the pins of a few cells. If I run it with a netlist that doesn't have those cells in it, the error appears on another one.

Expected Behavior

Complete pin_access and go forward with global routing.

Environment

[WARNING] Your current OpenROAD version is outdated.
It is recommened to pull the latest changes.
If problem persists, file a github issue with the re-producible test case.
kernel: Linux 3.10.0-1160.88.1.el7.x86_64
os: Ubuntu 22.04.2 LTS (Jammy Jellyfish)
cmake version 3.24.2
-- The CXX compiler identification is GNU 11.3.0
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Check for working CXX compiler: /usr/bin/c++ - skipped
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- OpenROAD version: v2.0-9405-g9b378ff51
-- System name: Linux
-- Compiler: GNU 11.3.0
-- Build type: RELEASE
-- Install prefix: /usr/local
-- C++ Standard: 17
-- C++ Standard Required: ON
-- C++ Extensions: OFF
-- The C compiler identification is GNU 11.3.0
-- Detecting C compiler ABI info
-- Detecting C compiler ABI info - done
-- Check for working C compiler: /usr/bin/cc - skipped
-- Detecting C compile features
-- Detecting C compile features - done
-- Found Python: /usr/bin/python3.10 (found version "3.10.6") found components: Interpreter 
-- Performing Test CMAKE_HAVE_LIBC_PTHREAD
-- Performing Test CMAKE_HAVE_LIBC_PTHREAD - Success
-- Found Threads: TRUE  
-- Performing Test C_COMPILER_SUPPORTS__-Wall
-- Performing Test C_COMPILER_SUPPORTS__-Wall - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wall
-- Performing Test CXX_COMPILER_SUPPORTS__-Wall - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-array-bounds
-- Performing Test C_COMPILER_SUPPORTS__-Wno-array-bounds - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-array-bounds
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-array-bounds - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-nonnull
-- Performing Test C_COMPILER_SUPPORTS__-Wno-nonnull - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-nonnull
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-nonnull - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-maybe-uninitialized
-- Performing Test C_COMPILER_SUPPORTS__-Wno-maybe-uninitialized - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-maybe-uninitialized
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-maybe-uninitialized - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-format-overflow
-- Performing Test C_COMPILER_SUPPORTS__-Wno-format-overflow - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-format-overflow
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-format-overflow - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-unused-variable
-- Performing Test C_COMPILER_SUPPORTS__-Wno-unused-variable - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-unused-variable
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-unused-variable - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-unused-function
-- Performing Test C_COMPILER_SUPPORTS__-Wno-unused-function - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-unused-function
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-unused-function - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-write-strings
-- Performing Test C_COMPILER_SUPPORTS__-Wno-write-strings - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-write-strings
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-write-strings - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-sign-compare
-- Performing Test C_COMPILER_SUPPORTS__-Wno-sign-compare - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-sign-compare
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-sign-compare - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-deprecated
-- Performing Test C_COMPILER_SUPPORTS__-Wno-deprecated - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-deprecated
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-deprecated - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-c++11-narrowing
-- Performing Test C_COMPILER_SUPPORTS__-Wno-c++11-narrowing - Failed
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-c++11-narrowing
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-c++11-narrowing - Failed
-- Performing Test C_COMPILER_SUPPORTS__-Wno-register
-- Performing Test C_COMPILER_SUPPORTS__-Wno-register - Failed
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-register
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-register - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-format
-- Performing Test C_COMPILER_SUPPORTS__-Wno-format - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-format
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-format - Success
-- Performing Test C_COMPILER_SUPPORTS__-Wno-reserved-user-defined-literal
-- Performing Test C_COMPILER_SUPPORTS__-Wno-reserved-user-defined-literal - Failed
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-reserved-user-defined-literal
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-reserved-user-defined-literal - Failed
-- Performing Test C_COMPILER_SUPPORTS__-fpermissive
-- Performing Test C_COMPILER_SUPPORTS__-fpermissive - Failed
-- Performing Test CXX_COMPILER_SUPPORTS__-fpermissive
-- Performing Test CXX_COMPILER_SUPPORTS__-fpermissive - Success
-- Performing Test C_COMPILER_SUPPORTS__-x
-- Performing Test C_COMPILER_SUPPORTS__-x - Failed
-- Performing Test CXX_COMPILER_SUPPORTS__-x
-- Performing Test CXX_COMPILER_SUPPORTS__-x - Failed
-- Performing Test C_COMPILER_SUPPORTS__c++
-- Performing Test C_COMPILER_SUPPORTS__c++ - Failed
-- Performing Test CXX_COMPILER_SUPPORTS__c++
-- Performing Test CXX_COMPILER_SUPPORTS__c++ - Failed
-- Performing Test C_COMPILER_SUPPORTS__-Wno-unused-but-set-variable
-- Performing Test C_COMPILER_SUPPORTS__-Wno-unused-but-set-variable - Success
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-unused-but-set-variable
-- Performing Test CXX_COMPILER_SUPPORTS__-Wno-unused-but-set-variable - Success
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL readline library: /usr/lib/x86_64-linux-gnu/libtclreadline.so
-- TCL readline header: /usr/include/x86_64-linux-gnu
-- Found SWIG: /usr/local/bin/swig (found suitable version "4.1.0", minimum required is "3.0")  
-- Using SWIG >= 4.1.0 -flatstaticmethod flag for python
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0")  
-- boost: 1.80.0
-- Found Python3: /usr/include/python3.10 (found version "3.10.6") found components: Development Development.Module Development.Embed 
-- Found ZLIB: /usr/lib/x86_64-linux-gnu/libz.so (found version "1.2.11") 
-- spdlog: 1.8.1
-- Found BISON: /usr/bin/bison (found version "3.8.2") 
-- Could NOT find Doxygen (missing: DOXYGEN_EXECUTABLE) 
-- STA version: 2.4.0
-- STA git sha: 3275a304e17092895b7d7721148edc7dc67ba3aa
-- System name: Linux
-- Compiler: GNU 11.3.0
-- Build type: RELEASE
-- Build CXX_FLAGS: -O3 -DNDEBUG
-- Install prefix: /usr/local
-- Found FLEX: /usr/bin/flex (found version "2.6.4") 
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- SSTA: 0
-- STA executable: /home/OpenROAD/src/sta/app/sta
-- GPU is not enabled
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found re2: /opt/or-tools/lib/cmake/re2/re2Config.cmake (found version "9.0.0") 
-- Found Clp: /opt/or-tools/lib/cmake/Clp/ClpConfig.cmake (found version "1.17.7") 
-- Found Cbc: /opt/or-tools/lib/cmake/Cbc/CbcConfig.cmake (found version "2.10.7") 
-- Found Eigen3: /usr/local/share/eigen3/cmake/Eigen3Config.cmake (found version "3.4.0") 
-- Found SCIP: /opt/or-tools/lib/cmake/scip/scip-config.cmake (found version "8.0.1") 
-- GUI is enabled
-- Charts widget is not enabled
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization 
-- Found OpenMP_CXX: -fopenmp (found version "4.5") 
-- Found OpenMP: TRUE (found version "4.5")  
-- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS) 
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found suitable version "1.80.0", minimum required is "1.78")  
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization system thread 
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0")  
-- TCL readline enabled
-- Tcl Extended disabled
-- Python3 enabled
-- Configuring done
-- Generating done
-- Build files have been written to: /tmp/tmp.SubecTftTH

To Reproduce

I tried to create a testcase, unfortunately the routing worked there without errors. This doesn't really confuse me, because the routing also worked on many other instances with the same master (in the large design).

Relevant log output

OpenROAD v2.0-9405-g9b378ff51 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
############################################################################
##
## Copyright (c) 2019, The Regents of the University of California
## All rights reserved.
##
## BSD 3-Clause License
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
##   list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
##   this list of conditions and the following disclaimer in the documentation
##   and/or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
##   contributors may be used to endorse or promote products derived from
##   this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
############################################################################
# Assumes flow_helpers.tcl has been read.
read_libraries
[INFO ODB-0222] Reading LEF file: xh018_xx51_MET5_METMID.lef
[INFO ODB-0223]     Created 18 technology layers
[INFO ODB-0224]     Created 180 technology vias
[INFO ODB-0226] Finished LEF file:  xh018_xx51_MET5_METMID.lef
[INFO ODB-0222] Reading LEF file: xh018_D_CELLS_JIHD.lef
[INFO ODB-0225]     Created 769 library cells
[INFO ODB-0226] Finished LEF file:  xh018_D_CELLS_JIHD.lef
[INFO ODB-0222] Reading LEF file: ram/XSPRAMLP_128X16_M8P.lef
[INFO ODB-0225]     Created 1 library cells
[INFO ODB-0226] Finished LEF file:  ram/XSPRAMLP_128X16_M8P.lef
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 318, wireload 0_1k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 319, wireload 0_5k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 320, wireload 1k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 321, wireload 2k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 322, wireload 5k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 323, wireload 10k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 324, wireload 30k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 325, wireload 50k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 326, wireload 100k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 327, wireload 200k not found.
[WARNING STA-0072] D_CELLS_JIHD_LPMOS_slow_1_62V_125C.lib line 328, wireload 500k not found.
read_verilog $synth_verilog
link_design $top_module
read_sdc $sdc_file
[WARNING STA-0354] set_input_delay relative to a clock defined on the same port/pin not allowed.
utl::metric "IFP::ord_version" [ord::openroad_git_describe]
# Note that sta::network_instance_count is not valid after tapcells are added.
utl::metric "IFP::instance_count" [sta::network_instance_count]
initialize_floorplan -site $site \
  -die_area $die_area \
  -core_area $core_area
[WARNING IFP-0028] Core area lower left (2.000, 2.000) snapped to (2.240, 4.480).
[INFO IFP-0001] Added 891 rows of 7135 site core_jihd with height 1.
#initialize_floorplan -utilization 60
#source $tracks_file
make_tracks
# remove buffers inserted by synthesis 
remove_buffers
[INFO RSZ-0026] Removed 39 buffers.
################################################################
# IO Placement (random)
place_pins -random -hor_layers $io_placer_hor_layer -ver_layers $io_placer_ver_layer
[WARNING PPL-0015] Macro RAM is not placed.
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
################################################################
# Macro Placement
if { [have_macros] } {
  global_placement -density $global_place_density
  macro_placement -halo $macro_place_halo -channel $macro_place_channel
}
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 560 4480
[INFO GPL-0004] CoreAreaLxLy: 2240 4480
[INFO GPL-0005] CoreAreaUxUy: 3997840 3996160
[INFO GPL-0006] NumInstances: 29390
[INFO GPL-0007] NumPlaceInstances: 29390
[INFO GPL-0008] NumFixedInstances: 0
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 34371
[INFO GPL-0011] NumPins: 117679
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 4000000 4000000
[INFO GPL-0014] CoreAreaLxLy: 2240 4480
[INFO GPL-0015] CoreAreaUxUy: 3997840 3996160
[INFO GPL-0016] CoreArea: 15949156608000
[INFO GPL-0017] NonPlaceInstsArea: 0
[INFO GPL-0018] PlaceInstsArea: 834525765950
[INFO GPL-0019] Util(%): 5.23
[INFO GPL-0020] StdInstsArea: 791343257600
[INFO GPL-0021] MacroInstsArea: 43182508350
[InitialPlace]  Iter: 1 CG residual: 0.00032145 HPWL: 670914020
[InitialPlace]  Iter: 2 CG residual: 0.00007291 HPWL: 687134572
[InitialPlace]  Iter: 3 CG residual: 0.00004967 HPWL: 694041091
[InitialPlace]  Iter: 4 CG residual: 0.00003838 HPWL: 698773770
[InitialPlace]  Iter: 5 CG residual: 0.00003505 HPWL: 700532122
[InitialPlace]  Iter: 6 CG residual: 0.00003898 HPWL: 702684678
[InitialPlace]  Iter: 7 CG residual: 0.00003281 HPWL: 703131035
[InitialPlace]  Iter: 8 CG residual: 0.00003467 HPWL: 704301918
[InitialPlace]  Iter: 9 CG residual: 0.00003405 HPWL: 704188325
[InitialPlace]  Iter: 10 CG residual: 0.00003685 HPWL: 704938975
[InitialPlace]  Iter: 11 CG residual: 0.00003656 HPWL: 704695045
[InitialPlace]  Iter: 12 CG residual: 0.00003518 HPWL: 705305771
[InitialPlace]  Iter: 13 CG residual: 0.00003372 HPWL: 704868510
[InitialPlace]  Iter: 14 CG residual: 0.00004098 HPWL: 705421148
[InitialPlace]  Iter: 15 CG residual: 0.00003432 HPWL: 704999369
[InitialPlace]  Iter: 16 CG residual: 0.00003866 HPWL: 705526024
[InitialPlace]  Iter: 17 CG residual: 0.00003715 HPWL: 705055783
[InitialPlace]  Iter: 18 CG residual: 0.00004221 HPWL: 705607178
[InitialPlace]  Iter: 19 CG residual: 0.00003393 HPWL: 705141382
[InitialPlace]  Iter: 20 CG residual: 0.00003655 HPWL: 705638580
[INFO GPL-0031] FillerInit: NumGCells: 184911
[INFO GPL-0032] FillerInit: NumGNets: 34371
[INFO GPL-0033] FillerInit: NumGPins: 117679
[INFO GPL-0023] TargetDensity: 0.30
[INFO GPL-0024] AveragePlaceInstArea: 28394888
[INFO GPL-0025] IdealBinArea: 94649624
[INFO GPL-0026] IdealBinCnt: 168507
[INFO GPL-0027] TotalBinArea: 15949156608000
[INFO GPL-0028] BinCnt: 256 256
[INFO GPL-0029] BinSize: 15608 15593
[INFO GPL-0030] NumBins: 65536
[NesterovSolve] Iter: 1 overflow: 0.981406 HPWL: 264623696
[NesterovSolve] Iter: 10 overflow: 0.97505 HPWL: 320742878
[NesterovSolve] Iter: 20 overflow: 0.974245 HPWL: 322991979
[NesterovSolve] Iter: 30 overflow: 0.973813 HPWL: 324779070
[NesterovSolve] Iter: 40 overflow: 0.973617 HPWL: 326215387
[NesterovSolve] Iter: 50 overflow: 0.973426 HPWL: 327557735
[NesterovSolve] Iter: 60 overflow: 0.973216 HPWL: 329094306
[NesterovSolve] Iter: 70 overflow: 0.973032 HPWL: 330675911
[NesterovSolve] Iter: 80 overflow: 0.972895 HPWL: 332109267
[NesterovSolve] Iter: 90 overflow: 0.972717 HPWL: 333232509
[NesterovSolve] Iter: 100 overflow: 0.972558 HPWL: 334095860
[NesterovSolve] Iter: 110 overflow: 0.972404 HPWL: 335044830
[NesterovSolve] Iter: 120 overflow: 0.972218 HPWL: 336626159
[NesterovSolve] Iter: 130 overflow: 0.971929 HPWL: 339632359
[NesterovSolve] Iter: 140 overflow: 0.971375 HPWL: 345307063
[NesterovSolve] Iter: 150 overflow: 0.970391 HPWL: 355229850
[NesterovSolve] Iter: 160 overflow: 0.969008 HPWL: 370849708
[NesterovSolve] Iter: 170 overflow: 0.966285 HPWL: 393100754
[NesterovSolve] Iter: 180 overflow: 0.962265 HPWL: 422299524
[NesterovSolve] Iter: 190 overflow: 0.954953 HPWL: 458960768
[NesterovSolve] Iter: 200 overflow: 0.944997 HPWL: 505034352
[NesterovSolve] Iter: 210 overflow: 0.931189 HPWL: 563808925
[NesterovSolve] Iter: 220 overflow: 0.91348 HPWL: 637240576
[NesterovSolve] Iter: 230 overflow: 0.893055 HPWL: 722229913
[NesterovSolve] Iter: 240 overflow: 0.870864 HPWL: 815479176
[NesterovSolve] Iter: 250 overflow: 0.843194 HPWL: 912969869
[NesterovSolve] Iter: 260 overflow: 0.814284 HPWL: 1000419836
[NesterovSolve] Iter: 270 overflow: 0.783119 HPWL: 1092039954
[NesterovSolve] Iter: 280 overflow: 0.746007 HPWL: 1330779568
[NesterovSolve] Iter: 290 overflow: 0.708661 HPWL: 1463091081
[NesterovSolve] Iter: 300 overflow: 0.683959 HPWL: 1379663995
[NesterovSolve] Iter: 310 overflow: 0.646678 HPWL: 1578609415
[NesterovSolve] Iter: 320 overflow: 0.622624 HPWL: 1468005965
[NesterovSolve] Iter: 330 overflow: 0.583264 HPWL: 1602100646
[NesterovSolve] Iter: 340 overflow: 0.551234 HPWL: 1568762776
[NesterovSolve] Iter: 350 overflow: 0.514764 HPWL: 1544487299
[NesterovSolve] Iter: 360 overflow: 0.473554 HPWL: 1586534981
[NesterovSolve] Iter: 370 overflow: 0.431942 HPWL: 1595472842
[NesterovSolve] Iter: 380 overflow: 0.386275 HPWL: 1613352275
[NesterovSolve] Iter: 390 overflow: 0.336718 HPWL: 1634301765
[NesterovSolve] Iter: 400 overflow: 0.298934 HPWL: 1646888211
[NesterovSolve] Iter: 410 overflow: 0.260414 HPWL: 1664463502
[NesterovSolve] Iter: 420 overflow: 0.22344 HPWL: 1682589529
[NesterovSolve] Iter: 430 overflow: 0.19207 HPWL: 1700160799
[NesterovSolve] Iter: 440 overflow: 0.162355 HPWL: 1714955105
[NesterovSolve] Iter: 450 overflow: 0.137308 HPWL: 1726518888
[NesterovSolve] Iter: 460 overflow: 0.116057 HPWL: 1734886537
[NesterovSolve] Finished with Overflow: 0.099484
[INFO MPL-0101] Found 1 macros.
[INFO MPL-0102] West pins 12.
[INFO MPL-0102] East pins 12.
[INFO MPL-0102] North pins 11.
[INFO MPL-0102] South pins 11.
[INFO MPL-0069] Initial weighted wire length 52842.
Begin one level partition.
[INFO MPL-0076] Partition 1 macros.
[INFO MPL-0077] Using 1 cut lines.
[INFO MPL-0079] Cut line 892.08.
End one level partition.
Begin horizontal partition.
Begin east partition.
[INFO MPL-0076] Partition 0 macros.
[INFO MPL-0077] Using 0 cut lines.
End east partition.
Begin west partition.
[INFO MPL-0076] Partition 1 macros.
[INFO MPL-0077] Using 1 cut lines.
[INFO MPL-0079] Cut line 1984.64.
End west partition.
End horizontal partition.
[INFO MPL-0070] Using 1 partition sets.
[INFO MPL-0071] Solution 1 weighted wire length 46269.8.
[INFO MPL-0073] Best weighted wire length 46269.8.
################################################################
# Tapcell insertion
#eval tapcell $tapcell_args
################################################################
# Power distribution network insertion
source $pdn_cfg
[WARNING ORD-0044] Net created for VDD, if intended as power or ground net add the -power/-ground switch as appropriate.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING ORD-0044] Net created for VSS, if intended as power or ground net add the -power/-ground switch as appropriate.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING ORD-0046] -defer_connection has been deprecated.
[WARNING PDN-0231] RAM is not connected to any power/ground nets.
pdngen
[WARNING PDN-0189] Supply pin VDD18M of instance RAM is not connected to any net.
[WARNING PDN-0189] Supply pin VSSM of instance RAM is not connected to any net.
[INFO PDN-0001] Inserting grid: grid
################################################################
# Global placement
foreach layer_adjustment $global_routing_layer_adjustments {
  lassign $layer_adjustment layer adjustment
  set_global_routing_layer_adjustment $layer $adjustment
}
set_routing_layers -signal $global_routing_layers \
  -clock $global_routing_clock_layers
#set_macro_extension 2
global_placement -routability_driven -density $global_place_density \
  -pad_left $global_place_pad -pad_right $global_place_pad
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 560 4480
[INFO GPL-0004] CoreAreaLxLy: 2240 4480
[INFO GPL-0005] CoreAreaUxUy: 3997840 3996160
[INFO GPL-0006] NumInstances: 29390
[INFO GPL-0007] NumPlaceInstances: 29389
[INFO GPL-0008] NumFixedInstances: 1
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 34373
[INFO GPL-0011] NumPins: 117679
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 4000000 4000000
[INFO GPL-0014] CoreAreaLxLy: 2240 4480
[INFO GPL-0015] CoreAreaUxUy: 3997840 3996160
[INFO GPL-0016] CoreArea: 15949156608000
[INFO GPL-0017] NonPlaceInstsArea: 44405760000
[INFO GPL-0018] PlaceInstsArea: 1381192243200
[INFO GPL-0019] Util(%): 8.68
[INFO GPL-0020] StdInstsArea: 1381192243200
[INFO GPL-0021] MacroInstsArea: 0
[InitialPlace]  Iter: 1 CG residual: 0.00198761 HPWL: 2300151964
[InitialPlace]  Iter: 2 CG residual: 0.00135965 HPWL: 797295189
[InitialPlace]  Iter: 3 CG residual: 0.00028927 HPWL: 803644534
[InitialPlace]  Iter: 4 CG residual: 0.00014356 HPWL: 807828552
[InitialPlace]  Iter: 5 CG residual: 0.00007335 HPWL: 808451788
[InitialPlace]  Iter: 6 CG residual: 0.00099316 HPWL: 809748568
[InitialPlace]  Iter: 7 CG residual: 0.00006764 HPWL: 809512782
[InitialPlace]  Iter: 8 CG residual: 0.00007821 HPWL: 809361433
[InitialPlace]  Iter: 9 CG residual: 0.00006709 HPWL: 807847190
[InitialPlace]  Iter: 10 CG residual: 0.00009173 HPWL: 806547923
[InitialPlace]  Iter: 11 CG residual: 0.00006075 HPWL: 803998096
[InitialPlace]  Iter: 12 CG residual: 0.00005751 HPWL: 802236133
[InitialPlace]  Iter: 13 CG residual: 0.00005550 HPWL: 799611786
[InitialPlace]  Iter: 14 CG residual: 0.00005449 HPWL: 798355248
[InitialPlace]  Iter: 15 CG residual: 0.00004862 HPWL: 797014285
[InitialPlace]  Iter: 16 CG residual: 0.00004990 HPWL: 796831137
[InitialPlace]  Iter: 17 CG residual: 0.00003937 HPWL: 795865322
[InitialPlace]  Iter: 18 CG residual: 0.00004020 HPWL: 796157094
[InitialPlace]  Iter: 19 CG residual: 0.00004537 HPWL: 795499415
[InitialPlace]  Iter: 20 CG residual: 0.00004270 HPWL: 795790729
[INFO GPL-0031] FillerInit: NumGCells: 103638
[INFO GPL-0032] FillerInit: NumGNets: 34373
[INFO GPL-0033] FillerInit: NumGPins: 117679
[INFO GPL-0023] TargetDensity: 0.30
[INFO GPL-0024] AveragePlaceInstArea: 46996911
[INFO GPL-0025] IdealBinArea: 156656368
[INFO GPL-0026] IdealBinCnt: 101809
[INFO GPL-0027] TotalBinArea: 15949156608000
[INFO GPL-0028] BinCnt: 256 256
[INFO GPL-0029] BinSize: 15608 15593
[INFO GPL-0030] NumBins: 65536
[NesterovSolve] Iter: 1 overflow: 0.996429 HPWL: 355930692
[NesterovSolve] Iter: 10 overflow: 0.989193 HPWL: 469097322
[NesterovSolve] Iter: 20 overflow: 0.985593 HPWL: 488367006
[NesterovSolve] Iter: 30 overflow: 0.984234 HPWL: 510056519
[NesterovSolve] Iter: 40 overflow: 0.983744 HPWL: 528837781
[NesterovSolve] Iter: 50 overflow: 0.983142 HPWL: 542924082
[NesterovSolve] Iter: 60 overflow: 0.982462 HPWL: 553403539
[NesterovSolve] Iter: 70 overflow: 0.982004 HPWL: 562636916
[NesterovSolve] Iter: 80 overflow: 0.981583 HPWL: 571440850
[NesterovSolve] Iter: 90 overflow: 0.981272 HPWL: 577756109
[NesterovSolve] Iter: 100 overflow: 0.981219 HPWL: 579972293
[NesterovSolve] Iter: 110 overflow: 0.981027 HPWL: 578722036
[NesterovSolve] Iter: 120 overflow: 0.981059 HPWL: 575765264
[NesterovSolve] Iter: 130 overflow: 0.981049 HPWL: 572603491
[NesterovSolve] Iter: 140 overflow: 0.981059 HPWL: 570455824
[NesterovSolve] Iter: 150 overflow: 0.980541 HPWL: 570473083
[NesterovSolve] Iter: 160 overflow: 0.979881 HPWL: 573945160
[NesterovSolve] Iter: 170 overflow: 0.978479 HPWL: 582886070
[NesterovSolve] Iter: 180 overflow: 0.975853 HPWL: 600482879
[NesterovSolve] Iter: 190 overflow: 0.97138 HPWL: 630788855
[NesterovSolve] Iter: 200 overflow: 0.963588 HPWL: 677258031
[NesterovSolve] Iter: 210 overflow: 0.951797 HPWL: 742022441
[NesterovSolve] Iter: 220 overflow: 0.936479 HPWL: 825222717
[NesterovSolve] Iter: 230 overflow: 0.918007 HPWL: 925611644
[NesterovSolve] Iter: 240 overflow: 0.897868 HPWL: 1042732077
[NesterovSolve] Iter: 250 overflow: 0.875085 HPWL: 1214691418
[NesterovSolve] Iter: 260 overflow: 0.846553 HPWL: 1455909537
[NesterovSolve] Iter: 270 overflow: 0.821584 HPWL: 1550364592
[NesterovSolve] Iter: 280 overflow: 0.7944 HPWL: 1694637283
[NesterovSolve] Iter: 290 overflow: 0.76219 HPWL: 1956075934
[NesterovSolve] Iter: 300 overflow: 0.737836 HPWL: 2034096311
[NesterovSolve] Iter: 310 overflow: 0.705466 HPWL: 1900887106
[NesterovSolve] Iter: 320 overflow: 0.671793 HPWL: 2137495277
[NesterovSolve] Iter: 330 overflow: 0.642783 HPWL: 2006120666
[NesterovSolve] Iter: 340 overflow: 0.604385 HPWL: 2154769959
[NesterovSolve] Snapshot saved at iter = 342
[NesterovSolve] Iter: 350 overflow: 0.570072 HPWL: 2181038640
[NesterovSolve] Iter: 360 overflow: 0.529108 HPWL: 2129962468
[NesterovSolve] Iter: 370 overflow: 0.48855 HPWL: 2131972875
[NesterovSolve] Iter: 380 overflow: 0.446185 HPWL: 2163728723
[NesterovSolve] Iter: 390 overflow: 0.396549 HPWL: 2158819959
[NesterovSolve] Iter: 400 overflow: 0.346227 HPWL: 2199752971
[NesterovSolve] Iter: 410 overflow: 0.306308 HPWL: 2214068414
[NesterovSolve] Iter: 420 overflow: 0.269183 HPWL: 2239621571
[NesterovSolve] Iter: 430 overflow: 0.23595 HPWL: 2260371917
[NesterovSolve] Iter: 440 overflow: 0.206448 HPWL: 2279118427
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
[INFO GPL-0036] TileLxLy: 0 0
[INFO GPL-0037] TileSize: 9150 9150
[INFO GPL-0038] TileCnt: 437 437
[INFO GPL-0039] numRoutingLayers: 6
[INFO GPL-0040] NumTiles: 190969
[INFO GPL-0063] TotalRouteOverflowH2: 0.0
[INFO GPL-0064] TotalRouteOverflowV2: 0.0
[INFO GPL-0065] OverflowTileCnt2: 0
[INFO GPL-0066] 0.5%RC: 0.9807501780758997
[INFO GPL-0067] 1.0%RC: 0.9361646944201113
[INFO GPL-0068] 2.0%RC: 0.8687962795367189
[INFO GPL-0069] 5.0%RC: 0.7382865659279392
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 0.9584574
[NesterovSolve] Iter: 450 overflow: 0.181059 HPWL: 2295265858
[NesterovSolve] Iter: 460 overflow: 0.158379 HPWL: 2306296409
[NesterovSolve] Iter: 470 overflow: 0.137404 HPWL: 2315479799
[NesterovSolve] Iter: 480 overflow: 0.118016 HPWL: 2323441284
[NesterovSolve] Iter: 490 overflow: 0.103056 HPWL: 2331136615
[NesterovSolve] Finished with Overflow: 0.099986
# IO Placement
place_pins -hor_layers $io_placer_hor_layer -ver_layers $io_placer_ver_layer
Found 1 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0010] Tentative 0 to set up sections.
[INFO PPL-0001] Number of slots          12908
[INFO PPL-0002] Number of I/O            46
[INFO PPL-0003] Number of I/O w/sink     46
[INFO PPL-0004] Number of I/O w/o sink   0
[INFO PPL-0005] Slots per section        200
[INFO PPL-0006] Slots increase factor    0.01
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 56084.16 um.
# checkpoint
set global_place_db [make_result_file ${design}_${platform}_global_place.db]
write_db $global_place_db
################################################################
# Repair max slew/cap/fanout violations and normalize slews
source $layer_rc_file
set_wire_rc -signal -layer $wire_rc_layer
set_wire_rc -clock  -layer $wire_rc_layer_clk
set_dont_use $dont_use
estimate_parasitics -placement
repair_design -slew_margin $slew_margin -cap_margin $cap_margin
[INFO RSZ-0058] Using max wire length 762um.
[INFO RSZ-0034] Found 96 slew violations.
[INFO RSZ-0037] Found 244 long wires.
[INFO RSZ-0038] Inserted 804 buffers in 246 nets.
[INFO RSZ-0039] Resized 4735 instances.
repair_tie_fanout -separation $tie_separation $tielo_port
[INFO RSZ-0042] Inserted 1 tie LOGIC0JIHD instances.
repair_tie_fanout -separation $tie_separation $tiehi_port
set_placement_padding -global -left $detail_place_pad -right $detail_place_pad
detailed_placement
Placement Analysis
---------------------------------
total displacement      61991.6 u
average displacement        2.1 u
max displacement           40.2 u
original HPWL         2384606.7 u
legalized HPWL        2411912.8 u
delta HPWL                    1 %

# post resize timing report (ideal clocks)
report_worst_slack -min -digits 3
worst slack 1.175
report_worst_slack -max -digits 3
worst slack 21.631
report_tns -digits 3
tns 0.000
# Check slew repair
report_check_types -max_slew -max_capacitance -max_fanout -violators
max slew

Pin                                    Limit    Slew   Slack
------------------------------------------------------------
RAM/WEn                                 5.00    5.53   -0.53 (VIOLATED)

utl::metric "RSZ::repair_design_buffer_count" [rsz::repair_design_buffer_count]
utl::metric "RSZ::max_slew_slack" [expr [sta::max_slew_check_slack_limit] * 100]
utl::metric "RSZ::max_fanout_slack" [expr [sta::max_fanout_check_slack_limit] * 100]
utl::metric "RSZ::max_capacitance_slack" [expr [sta::max_capacitance_check_slack_limit] * 100]
################################################################
# Clock Tree Synthesis
# Clone clock tree inverters next to register loads
# so cts does not try to buffer the inverted clocks.
repair_clock_inverters
clock_tree_synthesis -root_buf $cts_buffer -buf_list $cts_buffer \
  -sink_clustering_enable \
  -sink_clustering_max_diameter $cts_cluster_diameter
[INFO CTS-0049] Characterization buffer is: BUJIHDX4.
[INFO CTS-0039] Number of created patterns = 12240.
[INFO CTS-0084] Compiling LUT.
Min. len    Max. len    Min. cap    Max. cap    Min. slew   Max. slew
2           8           1           34          1           12          
[WARNING CTS-0043] 1632 wires are pure wire and no slew degradation.
TritonCTS forced slew degradation on these wires.
[INFO CTS-0046]     Number of wire segments: 9276.
[INFO CTS-0047]     Number of keys in characterization LUT: 1556.
[INFO CTS-0048]     Actual min input cap: 1.
[INFO CTS-0007] Net "clk" found for clock "CLK_ext".
[INFO CTS-0010]  Clock net "clk" has 5 sinks.
[WARNING CTS-0041] Net "net806" has 1 sinks. Skipping...
[INFO CTS-0010]  Clock net "rc_gclk" has 2898 sinks.
[INFO CTS-0008] TritonCTS found 2 clock nets.
[INFO CTS-0097] Characterization used 1 buffer(s) types.
[INFO CTS-0027] Generating H-Tree topology for net clk.
[INFO CTS-0028]  Total number of sinks: 5.
[INFO CTS-0029]  Sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um.
[INFO CTS-0030]  Number of static layers: 0.
[INFO CTS-0020]  Wire segment unit: 22000  dbu (22 um).
[INFO CTS-0023]  Original sink region: [(3727126, 3469915), (3760530, 3839430)].
[INFO CTS-0024]  Normalized sink region: [(169.415, 157.723), (170.933, 174.52)].
[INFO CTS-0025]     Width:  1.5184.
[INFO CTS-0026]     Height: 16.7961.
[WARNING CTS-0045] Creating fake entries in the LUT.
 Level 1
    Direction: Vertical
    Sinks per sub-region: 3
    Sub-region size: 1.5184 X 8.3981
[INFO CTS-0034]     Segment length (rounded): 4.
    Key: 24 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 4 delay: 5
      location: 1.0 buffer: BUJIHDX4
[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035]  Number of sinks covered: 5.
[INFO CTS-0027] Generating H-Tree topology for net rc_gclk.
[INFO CTS-0028]  Total number of sinks: 2898.
[INFO CTS-0029]  Sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um.
[INFO CTS-0030]  Number of static layers: 0.
[INFO CTS-0020]  Wire segment unit: 22000  dbu (22 um).
[INFO CTS-0019]  Total number of sinks after clustering: 519.
[INFO CTS-0024]  Normalized sink region: [(60.7557, 60.9232), (169.771, 178.01)].
[INFO CTS-0025]     Width:  109.0156.
[INFO CTS-0026]     Height: 117.0870.
 Level 1
    Direction: Vertical
    Sinks per sub-region: 260
    Sub-region size: 109.0156 X 58.5435
[INFO CTS-0034]     Segment length (rounded): 30.
    Key: 168 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 5
      location: 1.0 buffer: BUJIHDX4
    Key: 168 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 5
      location: 1.0 buffer: BUJIHDX4
    Key: 169 inSlew: 2 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 6
      location: 1.0 buffer: BUJIHDX4
    Key: 74 inSlew: 3 inCap: 1 outSlew: 1 load: 1 length: 6 delay: 7
      location: 1.0 buffer: BUJIHDX4
 Level 2
    Direction: Horizontal
    Sinks per sub-region: 130
    Sub-region size: 54.5078 X 58.5435
[INFO CTS-0034]     Segment length (rounded): 28.
    Key: 168 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 5
      location: 1.0 buffer: BUJIHDX4
    Key: 168 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 5
      location: 1.0 buffer: BUJIHDX4
    Key: 169 inSlew: 2 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 6
      location: 1.0 buffer: BUJIHDX4
    Key: 26 inSlew: 3 inCap: 1 outSlew: 1 load: 1 length: 4 delay: 7
      location: 1.0 buffer: BUJIHDX4
 Level 3
    Direction: Vertical
    Sinks per sub-region: 65
    Sub-region size: 54.5078 X 29.2717
[INFO CTS-0034]     Segment length (rounded): 14.
    Key: 168 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 5
      location: 1.0 buffer: BUJIHDX4
    Key: 72 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 6 delay: 5
      location: 1.0 buffer: BUJIHDX4
 Level 4
    Direction: Horizontal
    Sinks per sub-region: 33
    Sub-region size: 27.2539 X 29.2717
[INFO CTS-0034]     Segment length (rounded): 14.
    Key: 169 inSlew: 2 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 6
      location: 1.0 buffer: BUJIHDX4
    Key: 74 inSlew: 3 inCap: 1 outSlew: 1 load: 1 length: 6 delay: 7
      location: 1.0 buffer: BUJIHDX4
 Out of 63 sinks, 1 sinks closer to other cluster.
 Out of 66 sinks, 9 sinks closer to other cluster.
 Level 5
    Direction: Vertical
    Sinks per sub-region: 17
    Sub-region size: 27.2539 X 14.6359
[INFO CTS-0034]     Segment length (rounded): 8.
    Key: 168 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 8 delay: 5
      location: 1.0 buffer: BUJIHDX4
 Level 6
    Direction: Horizontal
    Sinks per sub-region: 9
    Sub-region size: 13.6270 X 14.6359
[INFO CTS-0034]     Segment length (rounded): 6.
    Key: 72 inSlew: 1 inCap: 1 outSlew: 1 load: 1 length: 6 delay: 5
      location: 1.0 buffer: BUJIHDX4
 Out of 15 sinks, 1 sinks closer to other cluster.
 Out of 18 sinks, 1 sinks closer to other cluster.
[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035]  Number of sinks covered: 519.
[INFO CTS-0018]     Created 3 clock buffers.
[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
[INFO CTS-0015]     Created 3 clock nets.
[INFO CTS-0016]     Fanout distribution for the current clock = 1:1, 4:1..
[INFO CTS-0017]     Max level of the clock tree: 1.
[INFO CTS-0018]     Created 646 clock buffers.
[INFO CTS-0012]     Minimum number of buffers in the clock path: 15.
[INFO CTS-0013]     Maximum number of buffers in the clock path: 16.
[INFO CTS-0015]     Created 646 clock nets.
[INFO CTS-0016]     Fanout distribution for the current clock = 2:51, 3:65, 4:63, 5:61, 6:59, 7:61, 8:59, 9:39, 10:34, 11:26, 12:13, 13:5, 14:5..
[INFO CTS-0017]     Max level of the clock tree: 6.
[INFO CTS-0098] Clock net "clk"
[INFO CTS-0099]  Sinks 5
[INFO CTS-0100]  Leaf buffers 0
[INFO CTS-0101]  Average sink wire length 632.96 um
[INFO CTS-0102]  Path depth 2 - 2
[INFO CTS-0098] Clock net "rc_gclk"
[INFO CTS-0099]  Sinks 2898
[INFO CTS-0100]  Leaf buffers 477
[INFO CTS-0101]  Average sink wire length 7000.98 um
[INFO CTS-0102]  Path depth 15 - 16
# CTS leaves a long wire from the pad to the clock tree root.
repair_clock_nets
[INFO RSZ-0058] Using max wire length 762um.
[INFO RSZ-0047] Found 1 long wires.
[INFO RSZ-0048] Inserted 2 buffers in 1 nets.
# place clock buffers
detailed_placement
Placement Analysis
---------------------------------
total displacement       1726.1 u
average displacement        0.1 u
max displacement            8.6 u
original HPWL         2516269.2 u
legalized HPWL        2516554.9 u
delta HPWL                    0 %

# checkpoint
set cts_db [make_result_file ${design}_${platform}_cts.db]
write_db $cts_db
################################################################
# Setup/hold timing repair
set_propagated_clock [all_clocks]
# Global routing is fast enough for the flow regressions.
# It is NOT FAST ENOUGH FOR PRODUCTION USE.
set repair_timing_use_grt_parasitics 0
if { $repair_timing_use_grt_parasitics } {
  # Global route for parasitics - no guide file requied
  global_route -congestion_iterations 100
  estimate_parasitics -global_routing
} else {
  estimate_parasitics -placement
}
repair_timing
[INFO RSZ-0046] Found 16 endpoints with hold violations.
[INFO RSZ-0032] Inserted 5 hold buffers.
# Post timing repair.
report_worst_slack -min -digits 3
worst slack 0.803
report_worst_slack -max -digits 3
worst slack 27.360
report_tns -digits 3
tns 0.000
report_check_types -max_slew -max_capacitance -max_fanout -violators -digits 3
max slew

Pin                                     Limit     Slew    Slack
---------------------------------------------------------------
RAM/CLK                                 3.000    5.474   -2.474 (VIOLATED)
RAM/WEn                                 5.000    5.495   -0.495 (VIOLATED)

utl::metric "RSZ::worst_slack_min" [sta::worst_slack -min]
utl::metric "RSZ::worst_slack_max" [sta::worst_slack -max]
utl::metric "RSZ::tns_max" [sta::total_negative_slack -max]
utl::metric "RSZ::hold_buffer_count" [rsz::hold_buffer_count]
################################################################
# Detailed Placement
detailed_placement
Placement Analysis
---------------------------------
total displacement          6.2 u
average displacement        0.0 u
max displacement            4.5 u
original HPWL         2516707.0 u
legalized HPWL        2516709.9 u
delta HPWL                    0 %

# Capture utilization before fillers make it 100%
utl::metric "DPL::utilization" [format %.1f [expr [rsz::utilization] * 100]]
utl::metric "DPL::design_area" [sta::format_area [rsz::design_area] 0]
# checkpoint
set dpl_db [make_result_file ${design}_${platform}_dpl.db]
write_db $dpl_db
set verilog_file [make_result_file ${design}_${platform}.v]
write_verilog $verilog_file
################################################################
# Global routing
pin_access -bottom_routing_layer $min_routing_layer \
           -top_routing_layer $max_routing_layer
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     770
Number of vias:       180
Number of viarulegen: 5

[INFO DRT-0150] Reading design.

Design:                   PS_Demo_core
Die area:                 ( 0 0 ) ( 4000000 4000000 )
Number of track patterns: 12
Number of DEF vias:       0
Number of components:     30850
Number of terminals:      46
Number of snets:          2
Number of nets:           35833

[INFO DRT-0167] List of default vias:
  Layer VIA1
    default via: VIA1_X_so
  Layer VIA2
    default via: VIA2_o
  Layer VIA3
    default via: VIA3_so
  Layer VIA4
    default via: VIA4_o
  Layer VIATP
    default via: VIATP_X_so
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
[INFO DRT-0164] Number of unique instances = 15193.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0024]   Complete POLY1.
[INFO DRT-0024]   Complete Fr_VIA.
[INFO DRT-0024]   Complete MET1.
[INFO DRT-0024]   Complete VIA1.
[INFO DRT-0024]   Complete MET2.
[INFO DRT-0024]   Complete VIA2.
[INFO DRT-0024]   Complete MET3.
[INFO DRT-0024]   Complete VIA3.
[INFO DRT-0024]   Complete MET4.
[INFO DRT-0024]   Complete VIA4.
[INFO DRT-0024]   Complete MET5.
[INFO DRT-0024]   Complete VIATP.
[INFO DRT-0024]   Complete METTP.
[INFO DRT-0033] POLY1 shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] MET1 shape region query size = 1146670.
[INFO DRT-0033] VIA1 shape region query size = 63610.
[INFO DRT-0033] MET2 shape region query size = 190857.
[INFO DRT-0033] VIA2 shape region query size = 63610.
[INFO DRT-0033] MET3 shape region query size = 190857.
[INFO DRT-0033] VIA3 shape region query size = 63610.
[INFO DRT-0033] MET4 shape region query size = 190928.
[INFO DRT-0033] VIA4 shape region query size = 63610.
[INFO DRT-0033] MET5 shape region query size = 190832.
[INFO DRT-0033] VIATP shape region query size = 63610.
[INFO DRT-0033] METTP shape region query size = 63754.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0077]   Complete 2000 pins.
[INFO DRT-0077]   Complete 3000 pins.
[INFO DRT-0077]   Complete 4000 pins.
[INFO DRT-0077]   Complete 5000 pins.
[INFO DRT-0077]   Complete 6000 pins.
[INFO DRT-0077]   Complete 7000 pins.
[INFO DRT-0077]   Complete 8000 pins.
[INFO DRT-0077]   Complete 9000 pins.
[INFO DRT-0077]   Complete 10000 pins.
[INFO DRT-0077]   Complete 11000 pins.
[INFO DRT-0077]   Complete 12000 pins.
[INFO DRT-0077]   Complete 13000 pins.
[INFO DRT-0077]   Complete 14000 pins.
[INFO DRT-0077]   Complete 15000 pins.
[INFO DRT-0077]   Complete 16000 pins.
[INFO DRT-0077]   Complete 17000 pins.
[INFO DRT-0077]   Complete 18000 pins.
[INFO DRT-0077]   Complete 19000 pins.
[INFO DRT-0077]   Complete 20000 pins.
[INFO DRT-0077]   Complete 21000 pins.
[INFO DRT-0077]   Complete 22000 pins.
[INFO DRT-0077]   Complete 23000 pins.
[INFO DRT-0077]   Complete 24000 pins.
[INFO DRT-0077]   Complete 25000 pins.
[INFO DRT-0077]   Complete 26000 pins.
[INFO DRT-0077]   Complete 27000 pins.
[INFO DRT-0077]   Complete 28000 pins.
[INFO DRT-0077]   Complete 29000 pins.
[INFO DRT-0077]   Complete 30000 pins.
[INFO DRT-0077]   Complete 31000 pins.
[INFO DRT-0077]   Complete 32000 pins.
[INFO DRT-0077]   Complete 33000 pins.
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[INFO DRT-0077]   Complete 40000 pins.
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[INFO DRT-0077]   Complete 43000 pins.
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[INFO DRT-0077]   Complete 46000 pins.
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[INFO DRT-0077]   Complete 54000 pins.
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[INFO DRT-0078]   Complete 56785 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0079]   Complete 400 unique inst patterns.
[INFO DRT-0079]   Complete 500 unique inst patterns.
[INFO DRT-0079]   Complete 600 unique inst patterns.
[INFO DRT-0079]   Complete 700 unique inst patterns.
[INFO DRT-0079]   Complete 800 unique inst patterns.
[INFO DRT-0079]   Complete 900 unique inst patterns.
[INFO DRT-0080]   Complete 1000 unique inst patterns.
[WARNING DRT-0087] No valid pattern for unique instance pipe_g54590__5477, master is AND4JIHDX0.
[INFO DRT-0080]   Complete 2000 unique inst patterns.
[INFO DRT-0080]   Complete 3000 unique inst patterns.
[INFO DRT-0080]   Complete 4000 unique inst patterns.
[INFO DRT-0080]   Complete 5000 unique inst patterns.
[INFO DRT-0080]   Complete 6000 unique inst patterns.
[INFO DRT-0080]   Complete 7000 unique inst patterns.
[INFO DRT-0080]   Complete 8000 unique inst patterns.
[INFO DRT-0080]   Complete 9000 unique inst patterns.
[INFO DRT-0080]   Complete 10000 unique inst patterns.
[INFO DRT-0080]   Complete 11000 unique inst patterns.
[INFO DRT-0080]   Complete 12000 unique inst patterns.
[WARNING DRT-0087] No valid pattern for unique instance pipe_g54134__2883, master is ON31JIHDX1.
[INFO DRT-0080]   Complete 13000 unique inst patterns.
[INFO DRT-0080]   Complete 14000 unique inst patterns.
[INFO DRT-0080]   Complete 15000 unique inst patterns.
[INFO DRT-0081]   Complete 15192 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
@@@ dead end inst
@@@ dead end inst
[ERROR DRT-0085] Valid access pattern combination not found for 
pipe_g54590__5477
@@@ dead end inst
@@@ dead end inst
[ERROR DRT-0085] Valid access pattern combination not found for 
pipe_g54134__2883
[INFO DRT-0083]   Complete 20000 groups.
[INFO DRT-0083]   Complete 30000 groups.
Error: flow.tcl, 197 DRT-0085

Screenshots

No response

Additional Context

Has anyone encountered this error before and know how to deal with it?

vijayank88 commented 1 year ago

@techstuds Which PDK it is?

techstuds commented 1 year ago

It's the XH018 PDK of X-FAB.

QuantamHD commented 1 year ago

OpenROAD is having a hard time accessing these cell.

[WARNING DRT-0087] No valid pattern for unique instance pipe_g54590__5477, master is AND4JIHDX0 [WARNING DRT-0087] No valid pattern for unique instance pipe_g54134__2883, master is ON31JIHDX1

The easiest thing to do would be to "not use" those cells. You can mark them dont_use in your liberty.

gadfort commented 1 year ago

I have a similar issue, delating to the number of vias the PA attempts. Here is my attempt to fix: https://github.com/The-OpenROAD-Project/OpenROAD/pull/3677 but this seems to have impacts on the routablity of the design so more work is needed. With this, I can get my designs to route in my PDK.

maliberty commented 1 year ago

What flow are you using? In ORFS you can use 'make global_route_issue' to package up your test case (assuming it is ok to share).

https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/etc/deltaDebug.py is useful for cutting down a large test case if needed.

osamahammad21 commented 1 year ago

@techstuds Is it ok to share the test case?

techstuds commented 1 year ago

@QuantamHD I've tried several times but the error still occurs until dont_use is ignored during synthesis (cells were marked as dont_use in SDC file before synthesis).

@gadfort Unfortunately, this didn't fix the error in my case, although it's a really promising change.

@maliberty I used the OpenROAD flow (not ORFS) in OpenROAD/test/flow.tcl because I'm mostly interested in P&R (the synthesis was done by Cadence Genus).

I've also tried to cutting down my testcase with deltaDebug.py but I'm probably doing something wrong here. In flow.tcl, a db file is written just before the pin_access step where the error occurs, so I used that db file. What do I need to pass as a step argument in this case? The command looks like this:

openroad -python deltaDebug.py --base_db_path test_dpl-tcl.db --error_string '[WARNING DRT-0087] No valid pattern for unique instance' --step step.sh --persistence 5

step.sh: pin_access -bottom_routing_layer MET2 -top_routing_layer METTP

maliberty commented 1 year ago

step.sh has to be a complete run of OR - you haven't loaded any odb to start with.

osamahammad21 commented 1 year ago

@techstuds recently we added support for extensive via search for access points that can't be accessed with the conventional openroad pin access technique. It solved the issue for peter. Could you try it again and tell us what you get. Also, if it is not solved yet, I think we need more information to work on this. At least some visuals on the pin that can't be accessed in relation to the routing tracks.

maliberty commented 9 months ago

Closing due to no response. If this is still relevant please reopen and update.