The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
https://theopenroadproject.org/
BSD 3-Clause "New" or "Revised" License
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"Guide not connected to design" with "SYNTHESIS_HIERARCHICAL = 1" #4340

Closed lustefan97 closed 11 months ago

lustefan97 commented 1 year ago

Describe the bug

Hello,

I have a design which has a known quantity of cells and that I want to use to build bigger and bigger "dummy" designs to perform some tests. To avoid a (rightful) optimization during synthesis I've set SYNTHESIS_HIERARCHICAL = 1 to allow having multiple time the same design in a top-level module. The problem I have at hand is that, during PnR with OpenROAD and a pin access check, I have a pin that is said "not visited" and then a "Guide not connected to design" error is raised, stopping the flow....

Expected Behavior

Hierarchical design routed without issue

Environment

I unfortunately cannot give the exact output as I do not have access to the machine on which I work for this script, but the version installed is the one from PR #4319

To Reproduce

TestCase.zip

Here is a test case, uncompress the file into OpenROAD-flow-scripts/tools/OpenROAD/test/, enter the TestCase directory and use bash run_adder_cst_pd.sh to reproduce the issue

Relevant log output

#--------------------------------------------------------------------#
#                              ROUTING                               #
#--------------------------------------------------------------------# 
# Step 1 : Global routing
#-----------------------------------------------------
pin_access -bottom_routing_layer $min_routing_layer \
           -top_routing_layer $max_routing_layer
set_global_routing_layer_adjustment $min_routing_layer-$max_routing_layer 0.3
set_routing_layers -signal $min_routing_layer-$max_routing_layer
set route_guide [make_result_file ${design}_${platform}.route_guide]
global_route -guide_file $route_guide \
             -congestion_iterations 100 \
             -allow_congestion
set_propagated_clock [all_clocks]
estimate_parasitics -global_routing
# Check and repair antenna
#-----------------------------------------------------
check_antennas
# Filler placement 
#-----------------------------------------------------
filler_placement $filler_cells
check_placement -verbose
# Step 2 : DETAILLED ROUTING
#------------------------------------------------------
pin_access -bottom_routing_layer $min_routing_layer \
           -top_routing_layer $max_routing_layer
set_thread_count [exec getconf _NPROCESSORS_ONLN]
detailed_route -output_drc [make_result_file "${design}_${platform}_route_drc.rpt"] \
              -output_maze [make_result_file "${design}_${platform}_maze.log"] \
              -no_pin_access \
              -save_guide_updates \
              -bottom_routing_layer $min_routing_layer \
              -top_routing_layer $max_routing_layer \
              -verbose 1 
write_guides [make_result_file "${design}_${platform}_output_guide.mod"]
set drv_count [detailed_route_num_drvs]
utl::metric "DRT::drv" $drv_count
check_antennas
utl::metric "DRT::ANT::errors" [ant::antenna_violation_count]
set_propagated_clock [all_clocks]

[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0140] SpacingRange unsupported.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.

Units:                1000
Number of layers:     21
Number of macros:     212
Number of vias:       9
Number of viarulegen: 11

[WARNING DRT-0204] Cut layer V0 has no default via defined.
[WARNING DRT-0204] Cut layer V0 has no default via defined.
.
.
.
.
[WARNING DRT-0204] Cut layer V0 has no default via defined.
[WARNING DRT-0204] message limit reached, this message will no longer print
[INFO DRT-0150] Reading design.

Design:                   micro_adder
Die area:                 ( 0 0 ) ( 103679 103679 )
Number of track patterns: 32
Number of DEF vias:       0
Number of components:     336794
Number of terminals:      3072
Number of snets:          2
Number of nets:           71838

[WARNING DRT-0240] CUT layer V3 does not have square single-cut via, cut layer width may be set incorrectly.
[WARNING DRT-0240] CUT layer V5 does not have square single-cut via, cut layer width may be set incorrectly.
[INFO DRT-0167] List of default vias:
  Layer V2
    default via: VIA23
  Layer V3
    default via: VIA34
  Layer V4
    default via: VIA45
  Layer V5
    default via: VIA56
  Layer V6
    default via: VIA67
  Layer V7
    default via: VIA78
  Layer V8
    default via: VIA89
  Layer V9
    default via: VIA9Pad
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
  Complete 200000 instances.
  Complete 300000 instances.
[INFO DRT-0164] Number of unique instances = 147.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0019]   Complete 200000 insts.
[INFO DRT-0019]   Complete 300000 insts.
[INFO DRT-0024]   Complete Active.
[INFO DRT-0024]   Complete V0.
[INFO DRT-0024]   Complete M1.
[INFO DRT-0024]   Complete V1.
[INFO DRT-0024]   Complete M2.
[INFO DRT-0024]   Complete V2.
[INFO DRT-0024]   Complete M3.
[INFO DRT-0024]   Complete V3.
[INFO DRT-0024]   Complete M4.
[INFO DRT-0024]   Complete V4.
[INFO DRT-0024]   Complete M5.
[INFO DRT-0024]   Complete V5.
[INFO DRT-0024]   Complete M6.
[INFO DRT-0024]   Complete V6.
[INFO DRT-0024]   Complete M7.
[INFO DRT-0024]   Complete V7.
[INFO DRT-0024]   Complete M8.
[INFO DRT-0024]   Complete V8.
[INFO DRT-0024]   Complete M9.
[INFO DRT-0024]   Complete V9.
[INFO DRT-0024]   Complete Pad.
[INFO DRT-0033] Active shape region query size = 0.
[INFO DRT-0033] V0 shape region query size = 0.
[INFO DRT-0033] M1 shape region query size = 1490772.
[INFO DRT-0033] V1 shape region query size = 1120591.
[INFO DRT-0033] M2 shape region query size = 31413.
[INFO DRT-0033] V2 shape region query size = 10179.
[INFO DRT-0033] M3 shape region query size = 20358.
[INFO DRT-0033] V3 shape region query size = 6786.
[INFO DRT-0033] M4 shape region query size = 16965.
[INFO DRT-0033] V4 shape region query size = 6786.
[INFO DRT-0033] M5 shape region query size = 6966.
[INFO DRT-0033] V5 shape region query size = 324.
[INFO DRT-0033] M6 shape region query size = 180.
[INFO DRT-0033] V6 shape region query size = 0.
[INFO DRT-0033] M7 shape region query size = 0.
[INFO DRT-0033] V7 shape region query size = 0.
[INFO DRT-0033] M8 shape region query size = 0.
[INFO DRT-0033] V8 shape region query size = 0.
[INFO DRT-0033] M9 shape region query size = 3072.
[INFO DRT-0033] V9 shape region query size = 0.
[INFO DRT-0033] Pad shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0078]   Complete 532 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0081]   Complete 139 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
[INFO DRT-0084]   Complete 15164 groups.
#scanned instances     = 336794
#unique  instances     = 145
#stdCellGenAp          = 3958
#stdCellValidPlanarAp  = 48
#stdCellValidViaAp     = 3206
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 191990
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:32:34, elapsed time = 00:32:34, memory = 1130.54 (MB), peak = 1135.81 (MB)
[WARNING STA-0357] virtual clock clk can not be propagated.
[WARNING GRT-0026] Missing route to pin a1/_08384_/A.
[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.
[INFO DPL-0001] Placed 0 filler instances.
[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0140] SpacingRange unsupported.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.

Units:                1000
Number of layers:     21
Number of macros:     212
Number of vias:       9
Number of viarulegen: 11

[INFO DRT-0150] Reading design.

Design:                   micro_adder
Die area:                 ( 0 0 ) ( 103679 103679 )
Number of track patterns: 32
Number of DEF vias:       0
Number of components:     336794
Number of terminals:      3072
Number of snets:          2
Number of nets:           71838

[WARNING DRT-0240] CUT layer V3 does not have square single-cut via, cut layer width may be set incorrectly.
[WARNING DRT-0240] CUT layer V5 does not have square single-cut via, cut layer width may be set incorrectly.
[INFO DRT-0167] List of default vias:
  Layer V2
    default via: VIA23
  Layer V3
    default via: VIA34
  Layer V4
    default via: VIA45
  Layer V5
    default via: VIA56
  Layer V6
    default via: VIA67
  Layer V7
    default via: VIA78
  Layer V8
    default via: VIA89
  Layer V9
    default via: VIA9Pad
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
  Complete 200000 instances.
  Complete 300000 instances.
[INFO DRT-0164] Number of unique instances = 147.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0019]   Complete 200000 insts.
[INFO DRT-0019]   Complete 300000 insts.
[INFO DRT-0024]   Complete Active.
[INFO DRT-0024]   Complete V0.
[INFO DRT-0024]   Complete M1.
[INFO DRT-0024]   Complete V1.
[INFO DRT-0024]   Complete M2.
[INFO DRT-0024]   Complete V2.
[INFO DRT-0024]   Complete M3.
[INFO DRT-0024]   Complete V3.
[INFO DRT-0024]   Complete M4.
[INFO DRT-0024]   Complete V4.
[INFO DRT-0024]   Complete M5.
[INFO DRT-0024]   Complete V5.
[INFO DRT-0024]   Complete M6.
[INFO DRT-0024]   Complete V6.
[INFO DRT-0024]   Complete M7.
[INFO DRT-0024]   Complete V7.
[INFO DRT-0024]   Complete M8.
[INFO DRT-0024]   Complete V8.
[INFO DRT-0024]   Complete M9.
[INFO DRT-0024]   Complete V9.
[INFO DRT-0024]   Complete Pad.
[INFO DRT-0033] Active shape region query size = 0.
[INFO DRT-0033] V0 shape region query size = 0.
[INFO DRT-0033] M1 shape region query size = 1490772.
[INFO DRT-0033] V1 shape region query size = 1120591.
[INFO DRT-0033] M2 shape region query size = 31413.
[INFO DRT-0033] V2 shape region query size = 10179.
[INFO DRT-0033] M3 shape region query size = 20358.
[INFO DRT-0033] V3 shape region query size = 6786.
[INFO DRT-0033] M4 shape region query size = 16965.
[INFO DRT-0033] V4 shape region query size = 6786.
[INFO DRT-0033] M5 shape region query size = 6966.
[INFO DRT-0033] V5 shape region query size = 324.
[INFO DRT-0033] M6 shape region query size = 180.
[INFO DRT-0033] V6 shape region query size = 0.
[INFO DRT-0033] M7 shape region query size = 0.
[INFO DRT-0033] V7 shape region query size = 0.
[INFO DRT-0033] M8 shape region query size = 0.
[INFO DRT-0033] V8 shape region query size = 0.
[INFO DRT-0033] M9 shape region query size = 3072.
[INFO DRT-0033] V9 shape region query size = 0.
[INFO DRT-0033] Pad shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0078]   Complete 532 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0081]   Complete 139 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
[INFO DRT-0084]   Complete 15164 groups.
#scanned instances     = 336794
#unique  instances     = 145
#stdCellGenAp          = 3958
#stdCellValidPlanarAp  = 48
#stdCellValidViaAp     = 3206
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 191990
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:33:06, elapsed time = 00:33:07, memory = 1387.51 (MB), peak = 1394.30 (MB)
[INFO ORD-0030] Using 24 thread(s).
[INFO DRT-0156] guideIn read 100000 guides.
[INFO DRT-0156] guideIn read 200000 guides.
[INFO DRT-0156] guideIn read 300000 guides.
[INFO DRT-0156] guideIn read 400000 guides.

Number of guides:     490112

[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 191 STEP 540 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 191 STEP 540 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0026]   Complete 40000 origin guides.
[INFO DRT-0026]   Complete 50000 origin guides.
[INFO DRT-0026]   Complete 60000 origin guides.
[INFO DRT-0026]   Complete 70000 origin guides.
[INFO DRT-0026]   Complete 80000 origin guides.
[INFO DRT-0026]   Complete 90000 origin guides.
[INFO DRT-0027]   Complete 100000 origin guides.
[INFO DRT-0027]   Complete 200000 origin guides.
[INFO DRT-0027]   Complete 300000 origin guides.
[INFO DRT-0027]   Complete 400000 origin guides.
[INFO DRT-0028]   Complete Active.
[INFO DRT-0028]   Complete V0.
[INFO DRT-0028]   Complete M1.
[INFO DRT-0028]   Complete V1.
[INFO DRT-0028]   Complete M2.
[INFO DRT-0028]   Complete V2.
[INFO DRT-0028]   Complete M3.
[INFO DRT-0028]   Complete V3.
[INFO DRT-0028]   Complete M4.
[INFO DRT-0028]   Complete V4.
[INFO DRT-0028]   Complete M5.
[INFO DRT-0028]   Complete V5.
[INFO DRT-0028]   Complete M6.
[INFO DRT-0028]   Complete V6.
[INFO DRT-0028]   Complete M7.
[INFO DRT-0028]   Complete V7.
[INFO DRT-0028]   Complete M8.
[INFO DRT-0028]   Complete V8.
[INFO DRT-0028]   Complete M9.
[INFO DRT-0028]   Complete V9.
[INFO DRT-0028]   Complete Pad.
[WARNING DRT-0225] b[178] 1 pin not visited, fall back to feedthrough mode.
[WARNING DRT-0224] b[178] 1 pin not visited, number of guides = 32.
[ERROR DRT-0218] Guide is not connected to design.
Error: BottomDie.tcl, 273 DRT-0218

Screenshots

No response

Additional Context

No response

eder-matheus commented 1 year ago

@lustefan97 I've run this test case with the latest OpenROAD and the error is not happening anymore. We had a few fixes in GRT since the PR you mentioned, so it's possible that this issue was already fixed.

lustefan97 commented 1 year ago

I just updated OpenROAD-flow-scripts using build_openroad.sh --latest, when using etc/Env.sh it reports "Git commit: ed356f36fab23fcbf857925a0c04178d431b203f" which is the commit from the master branch yet I still have that exact same issue...

Although I do admit, this message did not seem to appear on another design (the same basically, but multiple one in a bigger top-level module), for reasons that I don't understand...

eder-matheus commented 1 year ago

@lustefan97 I did not have the error, but I see a weird behavior that is probably the cause for this error. The global router creates the guides correctly, with guides covering the pins placed at the top level, but the detailed router seems to modify the guides, removing this top layer guide. I'll investigate why this is happening.

eder-matheus commented 1 year ago

@lustefan97 I did not have the error, but I see a weird behavior that is probably the cause for this error. The global router creates the guides correctly, with guides covering the pins placed at the top level, but the detailed router seems to modify the guides, removing this top layer guide. I'll investigate why this is happening.

After debugging a little bit more, I noticed that it was not an issue. After creating the stack of vias to connect to the top layer pin, the detailed router will remove the top layer guides since it won't be needed anymore to proceed with the routing. I've tested it in CentOS and MacOS, and I don't have an error in any of them.

@lustefan97 Could you try running the attached files on the same machine you're having the issue with? Just unzip it and run openroad run.tcl. It should be using the same routing config from your run.

4340.zip

lustefan97 commented 12 months ago

@eder-matheus The files you gave me did work indeed, it is now going into the detailed routing optimization steps.

I don't really understand what is happening right now, if it was the OS I use an ubuntu 22.04 docker, which has never really gave me any trouble except for now...

eder-matheus commented 12 months ago

I don't really understand what is happening right now, if it was the OS I use an ubuntu 22.04 docker, which has never really gave me any trouble except for now...

Yeah, it seems really weird. Could you confirm the OpenROAD version when you run the binary? It should be in the beginning of the log. Perhaps you're compiling the correct version, but using another binary?

Also, the zip file you've sent me is the correct one? Maybe you attached the wrong file. I didn't see any reference to SYNTHESIS_HIERARCHICAL in the files you sent me.

lustefan97 commented 12 months ago

The version of OpenROAD reported when running the binary is OpenROAD v2.0-11343-ged356f36f (if this is what you meant, it is the very first thing that is reported when calling OpenROAD.

Regarding SYNTHESIS_HIERARCHICAL, to synthesize my modules I use the Yosys script used in the automatic flow (as I haven't managed to properly make a custom one, and I didn't want to waste more time than necessary on this step). Usually the test case that I send a related to OpenROAD and OpenROAD only, the .v file is the post synthesis RTL file (1_synth.v) from the automatic flow. What I do is that I synthesize the designs using the automatic scripts from ORFS, then move the result RTL into a custom director in OpenROAD/test/ to use it in a custom TCL script.

eder-matheus commented 12 months ago

@lustefan97 Got it. The commit looks correct, so I wonder why you have this DRT issue. The guides look fine, and DRT is appropriately processing them. My only guess is that I'm running a different version of your running, but I wonder if this is the case.

lustefan97 commented 12 months ago

@eder-matheus I think I figured it out.

It was a mistake on my part when uploading the test case. On my end I had modified the asap7_bottom.vars file to not perform any padding during GPL/DPL as it limits the maximum design utilization achievable by OpenROAD (as it stops everything when GPL detect a DU >100%). The "padding variables" were set at zero in my case where DRT fails, while it was still the "default" (global placement padding at 2 and detailed padding at 1) in the test case I sent you...

I attached a new TestCase file that should reproduce the issue, very sorry....

TestCase-2.zip

eder-matheus commented 12 months ago

@eder-matheus I think I figured it out.

It was a mistake on my part when uploading the test case. On my end I had modified the asap7_bottom.vars file to not perform any padding during GPL/DPL as it limits the maximum design utilization achievable by OpenROAD (as it stops everything when GPL detect a DU >100%). The "padding variables" were set at zero in my case where DRT fails, while it was still the "default" (global placement padding at 2 and detailed padding at 1) in the test case I sent you...

I attached a new TestCase file that should reproduce the issue, very sorry....

TestCase-2.zip

No problem! Thanks for the updated test case. I'll look at it soon.

lustefan97 commented 12 months ago

No problem! Thanks for the updated test case. I'll look at it soon.

Thank you ! I do have a few questions about those guides that I hope you can answer : What are they ? What do they do ? Why do we need them ? What are the difference in use between GRT and DRT regarding the guide ?

I'm curious to know

maliberty commented 12 months ago

Routing is hard problem so we divide it into two phases. The global router works on a coarse grid and ignores detailed DRC rules to give an overall solution that should be routable without congestion problems. It passes that solution to the detailed router in terms of a guide for each net. The guide give a set of layers/rectangles that tell the detailed router generally where to put the wires.

The detailed router tries to follow the guides while also dealing with all the detailed drc rules involved in making legal layout.

You can see the guides for a net in the GUI, after global routing, if you select a net and click 'Route Guides': image

lustefan97 commented 12 months ago

Oooh yes I remember now, thanks for the answer @maliberty !

lustefan97 commented 11 months ago

@eder-matheus Did you has the possibility to check the test case ? I am currently working on a project and having the flow working in this case would allow me to quickly perform more advanced tests, I am running a bit out of time and having it working would be amazing...

eder-matheus commented 11 months ago

A fix for it should come later today or at most, tomorrow. I'll let you know when the PR is created.

lustefan97 commented 11 months ago

@eder-matheus Sorry to insist... but has a PR been created for this issue ? I don't see anything explicitly related to it in the PR tab...

eder-matheus commented 11 months ago

No, it wasn't. The problem with this case is harder than we first thought, and now @arthurjolo is working to solve it.

lustefan97 commented 11 months ago

Ah I see, thank you !

eder-matheus commented 11 months ago

@lustefan97 Could you try latest master branch? We've merged the fix for this issue.