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The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
https://theopenroadproject.org/
BSD 3-Clause "New" or "Revised" License
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OpenROAD is crashing while starting FastRoute #457

Closed tamimcse closed 1 year ago

tamimcse commented 4 years ago

OpenROAD is crashing while starting FastRoute for https://github.com/tamimcse/test/blob/master/top.v. The Verilog is generated using Bambu HLS. The OpenROAD script is https://github.com/tamimcse/test/blob/master/bash_script.sh. The output is as following: You will see the crash at the very end.

`..... ...... yosys> opt_clean -purge

Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy.. Removed 96 unused cells and 9494 unused wires. <suppressed ~183 debug messages> y_typical.lib iberty /opt/panda/share/panda//nangate45/lib/NangateOpenCellLibrary

Printing statistics. === _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ===

Number of wires: 20066 Number of wire bits: 21196 Number of public wires: 2469 Number of public wire bits: 3599 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 18580 AND2_X1 1925 AND2_X2 49 AND2_X4 45 AND3_X1 488 AND3_X2 3 AND3_X4 6 AND4_X1 120 AND4_X2 3 AND4_X4 3 AOI211_X1 272 AOI211_X2 3 AOI21_X1 882 AOI21_X2 3 AOI221_X1 1 AOI221_X2 2 AOI221_X4 33 AOI22_X1 22 BUF_X1 4070 BUF_X16 2 BUF_X2 115 BUF_X4 273 BUF_X8 5 CLKBUF_X2 58 CLKBUF_X3 3 DFF_X1 1514 INV_X1 807 INV_X2 18 INV_X32 5 INV_X4 6 LOGIC0_X1 1 MUX2_X1 1143 MUX2_X2 4 NAND2_X1 1288 NAND2_X2 3 NAND2_X4 1 NAND3_X1 451 NAND3_X2 1 NAND4_X1 84 NAND4_X2 1 NOR2_X1 1262 NOR2_X2 11 NOR2_X4 9 NOR3_X1 335 NOR3_X2 1 NOR3_X4 1 NOR4_X1 58 NOR4_X2 2 NOR4_X4 2 OAI211_X1 356 OAI211_X2 3 OAI21_X1 615 OAI21_X2 1 OAI221_X1 44 OAI22_X1 30 OAI22_X2 1 OR2_X1 228 OR2_X2 5 OR2_X4 2 OR3_X1 236 OR4_X1 111 OR4_X2 1 XNOR2_X1 668 XOR2_X1 873 XOR2_X2 12

Chip area for module '_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy': 25630.164000

S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy_mapped.vPhPtS_PjS_S1_S_S1_S_S1

  1. Executing Verilog backend. Dumping module `_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy'.

yosys> exit

Warnings: 8 unique messages, 72 total End of script. Logfile hash: 9dd2f6b66b, CPU: user 35.81s system 0.18s, MEM: 104.99 MB peak Yosys 0.9+1706 (git sha1 b7419544, gcc 7.4.0-1ubuntu1~18.04.1 -fPIC -Os) Time spent: 28% 30x opt_clean (9 sec), 17% 25x opt_merge (6 sec), ... OpenROAD 1.1.0 484b8f0 License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'. Notice 0: Reading LEF file: OpenROAD_objects/merged.lef Notice 0: Created 22 technology layers Notice 0: Created 27 technology vias Notice 0: Created 134 library cells Notice 0: Finished LEF file: OpenROAD_objects/merged.lef Startpoint: 34756 (rising edge-triggered flip-flop clocked by clock) Endpoint: 36070 (rising edge-triggered flip-flop clocked by clock) Path Group: clock Path Type: max

Delay Time Description 0.00 0.00 clock clock (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ 34756/CK (DFF_X1) 0.08 0.08 ^ 34756/Q (DFF_X1) 0.17 0.26 ^ 30643/Z (BUF_X1) 0.02 0.28 v 17612/ZN (NOR2_X4) 0.05 0.33 v 17614/ZN (AND2_X4) 0.03 0.36 ^ 17703/ZN (NOR2_X2) 0.02 0.38 v 17719/ZN (INV_X1) 0.05 0.43 ^ 17720/ZN (AOI221_X2) 0.04 0.47 ^ 17721/ZN (AND2_X2) 0.03 0.50 ^ 17727/ZN (AND2_X4) 0.03 0.53 ^ 17749/ZN (AND2_X4) 0.03 0.56 ^ 17750/Z (BUF_X4) 0.04 0.59 ^ 21064/ZN (AND3_X4) 0.04 0.64 ^ 21069/ZN (AND3_X2) 0.04 0.67 ^ 21345/ZN (AND2_X4) 0.03 0.70 ^ 21451/Z (BUF_X8) 0.06 0.76 v 21452/Z (MUX2_X1) 0.03 0.79 v 21453/ZN (AND2_X1) 0.06 0.85 ^ 21456/ZN (AOI211_X2) 0.01 0.86 v 21467/ZN (NOR3_X1) 0.04 0.90 v 21487/ZN (OR2_X1) 0.06 0.96 v 21488/Z (MUX2_X1) 0.03 0.98 v 32559/Z (BUF_X1) 0.00 0.98 v 36070/D (DFF_X1) 0.98 data arrival time

1.00 1.00 clock clock (rise edge) 0.00 1.00 clock network delay (ideal) 0.00 1.00 clock reconvergence pessimism 1.00 ^ 36070/CK (DFF_X1) -0.04 0.96 library setup time 0.96 data required time 0.96 data required time -0.98 data arrival time -0.02 slack (VIOLATED) Design area 102521 u^2 100% utilization. Info: Added 428 rows of 3158 sites. WARNING: force pin spread option has no effect when using random pin placement

Running IO placement

Num of slots 7698 Num of I/O 1173 Num of I/O w/sink 1130 Num of I/O w/o sink 43 Slots Per Section 200 Slots Increase Factor 0.01 Usage Per Section 0.8 Usage Increase Factor 0.01 Force Pin Spread 1 WARNING: running random pin placement RandomMode Even

IO placement done. OpenROAD 1.1.0 484b8f0 License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'. Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef Notice 0: Created 22 technology layers Notice 0: Created 27 technology vias Notice 0: Created 134 library cells Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef Notice 0: Reading DEF file: OpenROAD_results/2_2_floorplan_io.def Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy Notice 0: Created 1173 pins. Notice 0: Created 18580 components and 95604 component-terminals. Notice 0: Created 21186 nets and 58444 connections. Notice 0: Finished DEF file: OpenROAD_results/2_2_floorplan_io.def invalid command name "STEP 3: Timing Driven Mixed Sized Placement" No macros found: Skipping global_placement fixIoPins.py : Fixing Pins in Def file Replacements made - West:337 South:249 East:338 North:249 fixIoPins.py : Finished OpenROAD 1.1.0 484b8f0 License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'. Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef Notice 0: Created 22 technology layers Notice 0: Created 27 technology vias Notice 0: Created 134 library cells Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef Notice 0: Reading DEF file: OpenROAD_results/2_3_floorplan_tdms.def Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy Notice 0: Created 1173 pins. Notice 0: Created 18580 components and 95604 component-terminals. Notice 0: Created 21186 nets and 58444 connections. Notice 0: Finished DEF file: OpenROAD_results/2_3_floorplan_tdms.def No macros found: Skipping macro_placement

Power Delivery Network Generator: Generating PDN

config: /opt/panda/share/panda//nangate45/pdn.cfg Design Name is _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy Reading BEOL LEF and gathering information ... ** INFO ** Type: stdcell, grid Stdcell Rails Layer: metal1 - Width: 0.170 Pitch: 2.400 Offset: 0.000 Straps Layer: metal4 - Width: 0.480 Pitch: 56.000 Offset: 2.000 Layer: metal7 - Width: 1.400 Pitch: 40.000 Offset: 2.000 Connect: {metal1 metal4} {metal4 metal7} Type: macro, macro_1 Macro orientation: R0 R180 MX MY Straps Layer: metal5 - Width: 0.930 Pitch: 40.000 Offset: 2.000 Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000 Connect: {metal4_PIN_ver metal5} {metal5 metal6} {metal6 metal7} Type: macro, macro_2 Macro orientation: R90 R270 MXR90 MYR90 Straps Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000 Connect: {metal4_PIN_hor metal6} {metal6 metal7} END INFO Inserting stdcell grid - grid Writing to database Running tapcell... Step 1: Cut rows... ---- Macro blocks found: 0 ---- #Original rows: 428 ---- #Cut rows: 0 Step 2: Insert endcaps... ---- #Endcaps inserted: 856 Step 3: Insert tapcells... ---- #Tapcells inserted: 860 Running tapcell... Done! [INFO] TargetDensity = 0.700000 mkdir: cannot create directory ‘/dev/null’: Not a directory mkdir: cannot create directory ‘/dev/null’: Not a directory mkdir: cannot create directory ‘/dev/null’: Not a directory mkdir: cannot create directory ‘/dev/null’: Not a directory mkdir: cannot create directory ‘/dev/null’: Not a directory mkdir: cannot create directory ‘/dev/null’: Not a directory [PROC] Begin Filling Replace Structure ... [INFO] DEF DBU = 2000 [INFO] RowHeight = 2800.000000 [INFO] ScaleDownUnit = 311.111115 [INFO] CoreAreaLxLy = (20140.000000, 22400.000000) [INFO] CoreAreaUxUy = (1220180.000000, 1220800.000000) [INFO] OffsetCoordi = (2260.000000, 0.000000) [INFO] ScaleDownRowHeight = 9.000000 [INFO] Modules = 18580 [INFO] Terminals = 2889 [PROC] Begin Generate Nets ... [INFO] NumNets = 21186 [INFO] NumPins = 59617 [PROC] End Generate Nets [INFO] Inserted Dummy Terms = 0 [PROC] Begin Generate Rows ... [INFO] RowSize = (1.221429, 9.000000) [INFO] NumRows = 428 [PROC] End Generate Rows [INFO] AspectRatio = 0.998633 [INFO] RowMinXY = (72.000000, 79.264282) [INFO] RowMaxXY = (3929.271240, 3931.264160) [INFO] NumPlaceStdCells = 18580 [INFO] NumPlaceMacros = 0 [INFO] RowSize = (1.221429, 9.000000) [INFO] NumRows = 428 [INFO] GlobalAreaLxLy = (7.489285, 7.489285) [INFO] GlobalAreaUxUy = (3993.717773, 3996.610596) [INFO] PlaceAreaLxLy = (72.000000, 79.264160) [INFO] PlaceAreaUxUy = (3929.271240, 3931.264160) [PROC] End Filling Replace Structure PROC: Conjugate Gradient (CG) method to obtain the IP INFO: The Initial HPWL is 524644.543317 INFO: The Matrix Size is 18580 INFO: IP 0, CG Error 0.000027, HPWL 545957.517281, CPUtime 0.17 INFO: IP 1, CG Error 0.000006, HPWL 526126.977911, CPUtime 0.21 INFO: IP 2, CG Error 0.000001, HPWL 523085.066241, CPUtime 0.22 INFO: IP 3, CG Error 0.000001, HPWL 522274.195831, CPUtime 0.21 INFO: IP 4, CG Error 0.000001, HPWL 521964.732325, CPUtime 0.19 INFO: IP 5, CG Error 0.000000, HPWL 521564.830225, CPUtime 0.21 ===HPWL(MICRON)==================================== Mode : Initial Placement HPWL : 735601.8216 x= 369036.8821 y= 366564.9395 [INFO] TotalPlaceArea = 14858209.000000 [INFO] TotalFixedArea = 18862.050781 [INFO] TotalWhiteSpaceArea = 14839347.000000 [INFO] TotalPlaceMacrosArea = 0.000000 [INFO] TotalPlaceStdCellsArea = 2692896.250000 [INFO] Util(%) = 18.123962 [INFO] 80pCellArea = 139.526581 [INFO] FillerInit: TotalFillerArea = 7694647.000000 [INFO] FillerInit: NumFillerCells = 55146 [INFO] FillerInit: FillerCellArea = 139.533539 [INFO] FillerInit: FillerCellSize = (15.503726, 9.000000) [INFO] FillerInit: NumCells = 73726 [INFO] FillerInit: NumModules = 18580 [INFO] FillerInit: NumFillers = 55146 INFO: D_MSH = 1024 INFO: MSH(X, Y) = (32, 32) INFO: dim_bin_cGP2D.(x,y) = (256, 256) cell Init 2D: tier->bin_stp: (15.0675 15.0469) tier->half_bin_stp: (7.5337 7.5234) PROC: Start NESTEROV's Optimization PROC: Global Lagrangian Multiplier is Applied [INFO] Timing: WNS = 1.29948e-11 [INFO] Timing: TNS = 0 [INFO] Nesterov: 0 OverFlow: 0.9854 ScaledHpwl: 3353720.0000 [INFO] Timing: WNS = -9.08862e-12 [INFO] Timing: TNS = -1.37044e-11 [INFO] Nesterov: 10 OverFlow: 0.7612 ScaledHpwl: 4656717.5000 [INFO] Nesterov: 20 OverFlow: 0.7271 ScaledHpwl: 4600205.0000 [INFO] Nesterov: 30 OverFlow: 0.7259 ScaledHpwl: 4532463.0000 [INFO] Nesterov: 40 OverFlow: 0.7285 ScaledHpwl: 4490022.5000 [INFO] Nesterov: 50 OverFlow: 0.7235 ScaledHpwl: 4512176.5000 [INFO] Nesterov: 60 OverFlow: 0.7214 ScaledHpwl: 4498370.5000 [INFO] Nesterov: 70 OverFlow: 0.7225 ScaledHpwl: 4486582.0000 [INFO] Nesterov: 80 OverFlow: 0.7223 ScaledHpwl: 4493103.0000 [INFO] Nesterov: 90 OverFlow: 0.7214 ScaledHpwl: 4493090.0000 [INFO] Nesterov: 100 OverFlow: 0.7219 ScaledHpwl: 4488126.0000 [INFO] Nesterov: 110 OverFlow: 0.7223 ScaledHpwl: 4489798.5000 [INFO] Nesterov: 120 OverFlow: 0.7219 ScaledHpwl: 4492216.0000 [INFO] Nesterov: 130 OverFlow: 0.7219 ScaledHpwl: 4491156.5000 [INFO] Nesterov: 140 OverFlow: 0.7219 ScaledHpwl: 4491949.0000 [INFO] Nesterov: 150 OverFlow: 0.7213 ScaledHpwl: 4494138.0000 [INFO] Nesterov: 160 OverFlow: 0.7207 ScaledHpwl: 4495404.0000 [INFO] Nesterov: 170 OverFlow: 0.7195 ScaledHpwl: 4498037.5000 [INFO] Nesterov: 180 OverFlow: 0.7177 ScaledHpwl: 4502708.0000 [INFO] Nesterov: 190 OverFlow: 0.7145 ScaledHpwl: 4507794.5000 [INFO] Nesterov: 200 OverFlow: 0.7106 ScaledHpwl: 4516302.0000 [INFO] Nesterov: 210 OverFlow: 0.7026 ScaledHpwl: 4528353.0000 [INFO] Nesterov: 220 OverFlow: 0.6926 ScaledHpwl: 4537470.5000 [INFO] Nesterov: 230 OverFlow: 0.6770 ScaledHpwl: 4543792.0000 [INFO] Nesterov: 240 OverFlow: 0.6535 ScaledHpwl: 4535685.5000 [INFO] Timing: WNS = -5.55014e-11 [INFO] Timing: TNS = -5.22214e-10 [INFO] Nesterov: 250 OverFlow: 0.6285 ScaledHpwl: 4530373.0000 [INFO] Nesterov: 260 OverFlow: 0.5989 ScaledHpwl: 4576544.0000 [INFO] Nesterov: 270 OverFlow: 0.5632 ScaledHpwl: 4603646.0000 [INFO] Nesterov: 280 OverFlow: 0.5264 ScaledHpwl: 4607634.0000 [INFO] Nesterov: 290 OverFlow: 0.4824 ScaledHpwl: 4654078.0000 [INFO] Timing: WNS = -1.06277e-10 [INFO] Timing: TNS = -2.22512e-09 [INFO] Nesterov: 300 OverFlow: 0.4519 ScaledHpwl: 4672081.0000 [INFO] Nesterov: 310 OverFlow: 0.4206 ScaledHpwl: 4691820.0000 [INFO] Nesterov: 320 OverFlow: 0.3851 ScaledHpwl: 4693493.0000 [INFO] Nesterov: 330 OverFlow: 0.3558 ScaledHpwl: 4698090.0000 [INFO] Nesterov: 340 OverFlow: 0.3219 ScaledHpwl: 4705394.0000 [INFO] Nesterov: 350 OverFlow: 0.2854 ScaledHpwl: 4708784.0000 [INFO] Timing: WNS = -1.50303e-10 [INFO] Timing: TNS = -2.67458e-09 [INFO] Nesterov: 360 OverFlow: 0.2545 ScaledHpwl: 4708413.0000 [INFO] Nesterov: 370 OverFlow: 0.2222 ScaledHpwl: 4707805.5000 [INFO] Timing: WNS = -1.4887e-10 [INFO] Timing: TNS = -2.59766e-09 [INFO] Nesterov: 380 OverFlow: 0.1903 ScaledHpwl: 4707631.5000 [INFO] Nesterov: 390 OverFlow: 0.1622 ScaledHpwl: 4708060.5000 [INFO] Nesterov: 400 OverFlow: 0.1380 ScaledHpwl: 4708762.5000 [INFO] Nesterov: 410 OverFlow: 0.1158 ScaledHpwl: 4712566.5000 [INFO] Nesterov: 420 OverFlow: 0.0998 ScaledHpwl: 4717579.5000 [INFO] Timing: WNS = -1.53279e-10 [INFO] Timing: TNS = -2.60917e-09 HP wire length: 731895 Worst slack: -1.53e-01 Total negative slack: -2.61e+00 Warning: cell 'OAI211_X1}' not found. Error: get_property is not an object. Inserted 1091 input buffers. Inserted 81 output buffers. Resized 5488 instances. Inserted 0 hold buffers. -------------------- Design Stats ------------------------------ core area : (20140, 22400) (1220180, 1220800) total cells : 21468 multi cells : 0 fixed cells : 1716 nets : 22360 design area : 1438127936000.000 total fixed area : 1825824000.000 total movable area : 284683840000.000 design utilization : 19.821 rows : 428 row height : 2800 Check Legality row check ==> PASS site check ==> PASS power check ==> PASS edge_check ==> PASS placed_check ==>> PASS overlap_check ==> PASS -------------------- Placement Analysis ------------------------ total displacement : 62095532 average displacement : 2892 max displacement : 66070 original HPWL : 738875.682 legalized HPWL : 752026.493 delta HPWL : 2% TritonCTS 2.0 * Current time: Thu Mar 19 22:26:59 2020

Import characterization * Reading LUT file "/opt/panda/share/panda//nangate45/tritonCTS/lut.txt" Min. len Max. len Min. cap Max. cap Min. slew Max. slew 2 8 1 52 1 24 [WARNING] 180 wires are pure wire and no slew degration. TritonCTS forced slew degradation on these wires. Num wire segments: 4994 Num keys in characterization LUT: 1677 Actual min input cap: 8 Reading solution list file "/opt/panda/share/panda//nangate45/tritonCTS/sol_list.txt"

Find clock roots * User did not specify clock roots. Using OpenSTA to find clock roots. Looking for clock sources... Clock names: clock

Populate TritonCTS * Initializing clock nets Number of user-input clocks: 1 ( "clock" ) Looking for clock nets in the design Net "clock" found clock

Check characterization The chacterization used 1 buffer(s) types. All of them are in the loaded DB. Build clock trees Generating H-Tree topology for net clock... Tot. number of sinks: 1514 Wire segment unit: 20000 dbu (10 um) Original sink region: [(231990, 315170), (972610, 919970)] Normalized sink region: [(12, 16), (49, 46)] Width: 37 Height: 30 Level 1 Direction: Horizontal

sinks per sub-region: 757

Sub-region size: 19 X 30 Segment length (rounded): 10 Key: 3192 outSlew: 1 load: 1 length: 8 isBuffered: 1 Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0 Level 2 Direction: Vertical

sinks per sub-region: 379

Sub-region size: 19 X 15 Segment length (rounded): 8 Key: 3206 outSlew: 1 load: 1 length: 8 isBuffered: 1 Level 3 Direction: Horizontal

sinks per sub-region: 190

Sub-region size: 9 X 15 Segment length (rounded): 4 Key: 1170 outSlew: 12 load: 1 length: 4 isBuffered: 1 Level 4 Direction: Vertical

sinks per sub-region: 95

Sub-region size: 9 X 8 Segment length (rounded): 4 Key: 1242 outSlew: 12 load: 1 length: 4 isBuffered: 1 Level 5 Direction: Horizontal

sinks per sub-region: 48

Sub-region size: 5 X 8 Segment length (rounded): 2 Key: 548 outSlew: 2 load: 1 length: 2 isBuffered: 1 [WARNING] Creating fake entries in the LUT. Level 6 Direction: Vertical

sinks per sub-region: 24

Sub-region size: 5 X 4 Segment length (rounded): 1 Key: 5029 outSlew: 12 load: 1 length: 1 isBuffered: 1 Level 7 Direction: Horizontal

sinks per sub-region: 12

Sub-region size: 2 X 4 Segment length (rounded): 1 Key: 5039 outSlew: 12 load: 1 length: 1 isBuffered: 1 Stop criterion found. Max number of sinks is (15) Building clock sub nets... Number of sinks covered: 1514 Clock topology of net "clock" done.

Post CTS opt * Avg. source sink dist: 46402 dbu. Num outlier sinks: 3

Write data to DB * Writing clock net "clock" to DB Created 258 clock buffers. Created 258 clock nets.

Current time: Thu Mar 19 22:26:59 2020 ... End of TritonCTS execution. -------------------- Design Stats ------------------------------ core area : (20140, 22400) (1220180, 1220800) total cells : 21726 multi cells : 0 fixed cells : 1716 nets : 22618 design area : 1438127936000.000 total fixed area : 1825824000.000 total movable area : 287720496000.000 design utilization : 20.032 rows : 428 row height : 2800 Check Legality row check ==> PASS site check ==> PASS power check ==> PASS edge_check ==> PASS placed_check ==>> PASS overlap_check ==> PASS -------------------- Placement Analysis ------------------------ total displacement : 1657681 average displacement : 76 max displacement : 16853 original HPWL : 763228.133 legalized HPWL : 763580.620 delta HPWL : 0% Adjust layer 2 in 70.0% Adjust layer 3 in 70.0% buffer overflow detected : openroad terminated`

eder-matheus commented 4 years ago

Hi, @tamimcse.

Are you generating the output files from each step (e.g: 3_placed.def after placement, 4_cts.def after clock tree synthesis, etc.)? If so, can you send me the input files for FastRoute?

tamimcse commented 4 years ago

I added the DEF files at https://github.com/tamimcse/test/tree/master/OpenROAD_results. I also updated the openroad script (https://github.com/tamimcse/test/blob/master/bash_script.sh). Please let me know if you need any other information.

eder-matheus commented 4 years ago

When I try to run "bash_script.sh", I get these following errors: ./bash_script.sh: 14: ./bash_script.sh: /scripts/mergeLef.py: not found ./bash_script.sh: 15: ./bash_script.sh: /scripts/padLefMacro.py: not found ./bash_script.sh: 16: ./bash_script.sh: /scripts/modifyLefSpacing.py: not found ./bash_script.sh: 17: ./bash_script.sh: /scripts/mergeLib.pl: not found ./bash_script.sh: 18: ./bash_script.sh: /scripts/markDontUse.py: not found

If you can send me these files, and if you can send me the LEF files used as input for FastRoute, it would be great

rovinski commented 4 years ago

@tamimcse if you use OpenROAD-flow, you can run make global_route_issue which will produce a tar.gz file with everything @eder-matheus needs to debug. Please browse the tar to make sure it doesn't package any proprietary / NDA materials or things you do not want to share. If you are able to reproduce the issue with nangate45 on an open-source netlist, then there should be no IP issues.

tamimcse commented 4 years ago

OK, never mind about the previous scripts. I added all the scripts in https://github.com/tamimcse/test/tree/master/sail_sim. Here you want to run synthesize_Synthesis__Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy.sh. It sets some environment variables, then runs HLS_output/Synthesis/bash_flow/bash_script.sh. This is the actual openroad script. It generates output in OpenROAD_results folder. Here you will find the intermediate DEF files. Please let me know if face any issue running it.

eder-matheus commented 4 years ago

I'm having some trouble running your script. Does it need to be run in a Docker or something like that? Also, do I need to clone and build the OpenROAD-flow at some place inside your repo?

tamimcse commented 4 years ago

No, you don't need OpenROAD-flow or docker at all. However you will need to install openroad, yosys and TritonRoute separately. Those binaries needs to be accessible via PATH variable (they are accessible by default).

Then you simply can clone https://github.com/tamimcse/test. Then enter test/sail_sim/ and then run sh synthesize_Synthesis__Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy.sh. This should run openroad.

Here we don't use the TCL scripts of OpenROAD-flow. We rather use shell script (HLS_output/Synthesis/bash_flow/bash_script.sh) which is analogous to OpenROAD-flow TCL scripts.

eder-matheus commented 4 years ago

Hi, @tamimcse.

Sorry for the delay with it. I spent the last days fixing some memory issues in FastRoute code, that was probably the cause of the crash that you are facing. Can you try to update your submodule of FastRoute with the last "openroad" branch updates?

tamimcse commented 4 years ago

Thanks @eder-matheus for looking into the issue!!!!

I updated OpenROAD to "openroad" branch along with all the sub-modules as following: git fetch origin git checkout -f --recurse-submodules origin/openroad

The new version is successfully compiled and installed . But I'm still getting the same error.

Note that if I change uint32_t C112[SIZE112] to uint8_t C112[SIZE112] in https://github.com/tamimcse/test/blob/master/module.cpp, the generated verilog works properly with OpenROAD. So I guess, it's causing error at some boundary condition or exceeding memory..

Current output is as following:

---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _34076_/CK (DFF_X1)
   0.08    0.08 ^ _34076_/Q (DFF_X1)
   0.21    0.29 ^ _31306_/Z (BUF_X1)
   0.05    0.35 v _20241_/ZN (INV_X1)
   0.07    0.42 v _20242_/Z (MUX2_X1)
   0.04    0.46 ^ _20243_/ZN (NOR2_X1)
   0.04    0.50 v _20244_/ZN (NAND3_X1)
   0.05    0.55 ^ _20246_/ZN (NOR2_X1)
   0.03    0.57 v _30089_/ZN (XNOR2_X1)
   0.03    0.60 v _30092_/ZN (AND2_X1)
   0.04    0.64 ^ _30094_/ZN (NOR2_X1)
   0.01    0.66 v _30097_/ZN (NOR2_X1)
   0.07    0.73 v _30103_/ZN (OR3_X1)
   0.02    0.74 ^ _30109_/ZN (NAND3_X1)
   0.04    0.78 ^ _30111_/ZN (AND2_X1)
   0.01    0.79 v _30114_/ZN (INV_X1)
   0.03    0.82 v _30115_/ZN (AND2_X1)
   0.04    0.85 ^ _30117_/ZN (NOR2_X1)
   0.01    0.86 v _30120_/ZN (INV_X1)
   0.03    0.89 v _30121_/ZN (AND2_X1)
   0.04    0.93 ^ _30123_/ZN (NOR2_X1)
   0.01    0.94 v _30126_/ZN (INV_X1)
   0.03    0.97 v _30127_/ZN (AND2_X1)
   0.03    1.00 ^ _30138_/ZN (OAI211_X1)
   0.04    1.04 ^ _30141_/ZN (AND2_X1)
   0.01    1.05 v _30146_/ZN (NOR3_X1)
   0.04    1.09 ^ _30147_/ZN (NOR2_X1)
   0.01    1.09 v _30151_/ZN (INV_X1)
   0.03    1.13 v _30152_/ZN (AND2_X1)
   0.04    1.16 ^ _30154_/ZN (NOR2_X1)
   0.01    1.18 v _30162_/ZN (INV_X1)
   0.02    1.19 ^ _30178_/ZN (NAND4_X1)
   0.05    1.24 ^ _30182_/ZN (AND2_X1)
   0.01    1.25 v _30191_/ZN (INV_X1)
   0.03    1.28 v _30208_/ZN (AND4_X1)
   0.04    1.32 ^ _30213_/ZN (NOR2_X1)
   0.01    1.33 v _30216_/ZN (INV_X1)
   0.04    1.37 v _30240_/ZN (AND4_X1)
   0.03    1.41 ^ _30257_/ZN (OAI211_X1)
   0.05    1.45 ^ _30259_/ZN (AND2_X1)
   0.01    1.46 v _30269_/ZN (INV_X1)
   0.03    1.50 v _30270_/ZN (AND3_X1)
   0.03    1.53 ^ _30276_/ZN (OAI21_X1)
   0.02    1.55 v _30279_/ZN (NAND2_X1)
   0.04    1.59 v _30281_/ZN (XNOR2_X1)
   0.03    1.61 v _33350_/Z (BUF_X1)
   0.00    1.61 v _34112_/D (DFF_X1)
           1.61   data arrival time

  10.00   10.00   clock clock (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ _34112_/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -1.61   data arrival time
---------------------------------------------------------
           8.35   slack (MET)

Design area 22338 u^2 100% utilization.
Info: Added 428 rows of 3158 sites.
WARNING: force pin spread option has no effect when using random pin placement
 > Running IO placement
 * Num of slots          15394
 * Num of I/O            1173
 * Num of I/O w/sink     1130
 * Num of I/O w/o sink   43
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement
RandomMode Even
 > IO placement done.
OpenROAD 1.1.0 10f3b9acb7
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  OpenROAD_objects/merged_padded.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  OpenROAD_objects/merged_padded.lef
Notice 0: 
Reading DEF file: OpenROAD_results/2_2_floorplan_io.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 17409 components and 91049 component-terminals.
Notice 0:     Created 19466 nets and 56231 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_2_floorplan_io.def
invalid command name "STEP"
No macros found: Skipping global_placement
fixIoPins.py : Fixing Pins in Def file
Replacements made - West:337 South:249 East:338 North:249
fixIoPins.py : Finished
OpenROAD 1.1.0 10f3b9acb7
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  OpenROAD_objects/merged_padded.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  OpenROAD_objects/merged_padded.lef
Notice 0: 
Reading DEF file: OpenROAD_results/2_3_floorplan_tdms.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 17409 components and 91049 component-terminals.
Notice 0:     Created 19466 nets and 56231 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_3_floorplan_tdms.def
No macros found: Skipping macro_placement
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /opt/panda/share/panda//nangate45/pdn.cfg
[INFO] [PDNG-0008] Design Name is _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: metal1 -  width: 0.170  pitch: 2.400  offset: 0.000 
    Straps
      Layer: metal4 -  width: 0.480  pitch: 56.000  offset: 2.000 
      Layer: metal7 -  width: 1.400  pitch: 40.000  offset: 2.000 
    Connect: {metal1 metal4} {metal4 metal7}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY
    Straps
      Layer: metal5 -  width: 0.930  pitch: 40.000  offset: 2.000 
      Layer: metal6 -  width: 0.930  pitch: 40.000  offset: 2.000 
    Connect: {metal4_PIN_ver metal5} {metal5 metal6} {metal6 metal7}
Type: macro, macro_2
    Macro orientation: R90 R270 MXR90 MYR90
    Straps
      Layer: metal6 -  width: 0.930  pitch: 40.000  offset: 2.000 
    Connect: {metal4_PIN_hor metal6} {metal6 metal7}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
Running tapcell...
Step 1: Cut rows...
---- Macro blocks found: 0
---- #Original rows: 428
---- #Cut rows: 0
Step 2: Insert endcaps...
---- #Endcaps inserted: 856
Step 3: Insert tapcells...
---- #Tapcells inserted: 860
Running tapcell... Done!
[INFO] DBU = 2000
[INFO] SiteSize = (380, 2800)
[INFO] CoreAreaLxLy = (20140, 22400)
[INFO] CoreAreaUxUy = (1220180, 1220800)
[INFO] NumInstances = 19125
[INFO] NumPlaceInstances = 17409
[INFO] NumFixedInstances = 1716
[INFO] NumDummyInstances = 0
[INFO] NumNets = 19466
[INFO] NumPins = 57404
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (1240300, 1241200)
[INFO] CoreAreaLxLy = (20140, 22400)
[INFO] CoreAreaUxUy = (1220180, 1220800)
[INFO] CoreArea = 1438127936000
[INFO] NonPlaceInstsArea = 1825824000
[INFO] PlaceInstsArea = 237538000000
[INFO] Util(%) = 16.538166
[INFO] StdInstsArea = 237538000000
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 5.52228e-05 HPWL: 1569160840
[InitialPlace]  Iter: 2 CG Error: 4.02264e-05 HPWL: 1219611974
[InitialPlace]  Iter: 3 CG Error: 4.07536e-05 HPWL: 1207505910
[InitialPlace]  Iter: 4 CG Error: 2.11109e-05 HPWL: 1194744199
[InitialPlace]  Iter: 5 CG Error: 3.63708e-06 HPWL: 1190679609
[INFO] FillerInit: NumGCells = 76082
[INFO] FillerInit: NumGNets = 19466
[INFO] FillerInit: NumGPins = 57404
[INFO] TargetDensity = 0.700000
[INFO] AveragePlaceInstArea = 13644551
[INFO] IdealBinArea = 19492216
[INFO] IdealBinCnt = 73779
[INFO] TotalBinArea = 1438127936000
[INFO] BinCnt = (256, 256)
[INFO] BinSize = (4688, 4682)
[INFO] NumBins = 65536
[NesterovSolve] Iter: 1 overflow: 0.964526 HPWL: 1036220622
[NesterovSolve] Iter: 10 overflow: 0.830565 HPWL: 1339885339
[NesterovSolve] Iter: 20 overflow: 0.825848 HPWL: 1303117475
[NesterovSolve] Iter: 30 overflow: 0.819748 HPWL: 1312621182
[NesterovSolve] Iter: 40 overflow: 0.819763 HPWL: 1307866028
[NesterovSolve] Iter: 50 overflow: 0.818867 HPWL: 1308254686
[NesterovSolve] Iter: 60 overflow: 0.819504 HPWL: 1307724202
[NesterovSolve] Iter: 70 overflow: 0.820079 HPWL: 1307567762
[NesterovSolve] Iter: 80 overflow: 0.820425 HPWL: 1307545423
[NesterovSolve] Iter: 90 overflow: 0.820436 HPWL: 1307552361
[NesterovSolve] Iter: 100 overflow: 0.81996 HPWL: 1307728474
[NesterovSolve] Iter: 110 overflow: 0.819682 HPWL: 1307794642
[NesterovSolve] Iter: 120 overflow: 0.819445 HPWL: 1308306437
[NesterovSolve] Iter: 130 overflow: 0.819083 HPWL: 1308768772
[NesterovSolve] Iter: 140 overflow: 0.81869 HPWL: 1309771193
[NesterovSolve] Iter: 150 overflow: 0.817734 HPWL: 1311639084
[NesterovSolve] Iter: 160 overflow: 0.816285 HPWL: 1314553239
[NesterovSolve] Iter: 170 overflow: 0.813562 HPWL: 1318759018
[NesterovSolve] Iter: 180 overflow: 0.809711 HPWL: 1325187385
[NesterovSolve] Iter: 190 overflow: 0.803913 HPWL: 1333757207
[NesterovSolve] Iter: 200 overflow: 0.795142 HPWL: 1344644878
[NesterovSolve] Iter: 210 overflow: 0.782059 HPWL: 1354888246
[NesterovSolve] Iter: 220 overflow: 0.763298 HPWL: 1360572001
[NesterovSolve] Iter: 230 overflow: 0.738809 HPWL: 1368005403
[NesterovSolve] Iter: 240 overflow: 0.707271 HPWL: 1388321838
[NesterovSolve] Iter: 250 overflow: 0.670973 HPWL: 1410634941
[NesterovSolve] Iter: 260 overflow: 0.627411 HPWL: 1417518611
[NesterovSolve] Iter: 270 overflow: 0.575522 HPWL: 1447558459
[NesterovSolve] Iter: 280 overflow: 0.541366 HPWL: 1463319187
[NesterovSolve] Iter: 290 overflow: 0.491534 HPWL: 1497530175
[NesterovSolve] Iter: 300 overflow: 0.456894 HPWL: 1499899544
[NesterovSolve] Iter: 310 overflow: 0.42316 HPWL: 1494621772
[NesterovSolve] Iter: 320 overflow: 0.387449 HPWL: 1495946159
[NesterovSolve] Iter: 330 overflow: 0.344574 HPWL: 1503991648
[NesterovSolve] Iter: 340 overflow: 0.319009 HPWL: 1500030974
[NesterovSolve] Iter: 350 overflow: 0.29366 HPWL: 1500165547
[NesterovSolve] Iter: 360 overflow: 0.26929 HPWL: 1500273933
[NesterovSolve] Iter: 370 overflow: 0.243193 HPWL: 1500573738
[NesterovSolve] Iter: 380 overflow: 0.219838 HPWL: 1501122293
[NesterovSolve] Iter: 390 overflow: 0.195448 HPWL: 1501909092
[NesterovSolve] Iter: 400 overflow: 0.175295 HPWL: 1502706957
[NesterovSolve] Iter: 410 overflow: 0.155015 HPWL: 1503792725
[NesterovSolve] Iter: 420 overflow: 0.136574 HPWL: 1504933822
[NesterovSolve] Iter: 430 overflow: 0.119692 HPWL: 1506120724
[NesterovSolve] Iter: 440 overflow: 0.105736 HPWL: 1502199782
[NesterovSolve] Finished with Overflow: 0.0992929
Warning: cell 'OAI211_X1}' not found.
Error: get_property  is not an object.
Error: -buffer_cell required for buffer insertion.
invalid command name "legalize_placement"
Inserted 1091 input buffers.
Inserted 81 output buffers.
Resized 5671 instances.
Inserted 0 hold buffers.
 *****************
 * TritonCTS 2.0 *
 *****************
 *****************************
 *  Import characterization  *
 *****************************
 Reading LUT file "/opt/panda/share/panda//nangate45/tritonCTS/lut.txt"
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          52           1          24
    [WARNING] 180 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 4994
    Num keys in characterization LUT: 1677
    Actual min input cap: 8
 Reading solution list file "/opt/panda/share/panda//nangate45/tritonCTS/sol_list.txt"
 **********************
 *  Find clock roots  *
 **********************
 User did not specify clock roots.
 Using OpenSTA to find clock roots.
 Looking for clock sources...
    Clock names: clock 
 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Number of user-input clocks: 1 ( "clock" )
 Looking for clock nets in the design
 Net "clock" found
clock
invalid command name "legalize_placement"
Adjust layer 2 in 70.0%
Adjust layer 3 in 70.0%
*** buffer overflow detected ***: openroad terminated
rovinski commented 4 years ago

Hi @tamimcse, you can use three tick marks ( ``` ) before and after text to create a multi-line code block. It helps with your log readability, thanks.

``` example example example ```

example
example
example
tamimcse commented 4 years ago

This error doesn't occur if compiler optimization is turned off. I compiled openroad using following command and it worked fine.

cmake -DCMAKE_BUILD_TYPE=DEBUG \
      -DCMAKE_C_FLAGS_DEBUG="-g -O0" \
      -DCMAKE_CXX_FLAGS_DEBUG="-g -O0"

Probably the error is occurring not due to exceeding memory but for other causes.

Few days ago, I encountered buffer overflow detected while working on an another project. It was working fine in the compiler unoptimized version, but when turn on compiler optimization, I got buffer overflow detected. The cause was as following:

int insert_something(int a) {
  //return statement is missing here.
  insert_something_inner (a);
}

int insert_something_inner(int a) {
  //body of the function
}

After adding the return statement, the buffer overflow detected error disappeared. I guess, FastRoute may have similar issue.

eder-matheus commented 4 years ago

I fixed a lot of memory issues in FastRoute. Are you facing this issue with the latest version of the repository?

tamimcse commented 4 years ago

Yeah, this issue still exists (if I use compiler optimization). Here is the output of openroad branch:

OpenROAD-Flow makefile, sdc and verilog would be found at https://github.com/tamimcse/test5

tamim@tamim-HP-ENVY-17-Notebook-PC:~/OpenROAD-flow/flow$ make
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/global_place.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_1_place_gp.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 21392 components and 100636 component-terminals.
Notice 0:     Created 5 special nets and 42784 connections.
Notice 0:     Created 21032 nets and 57852 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.def
[INFO] DBU = 2000
[INFO] SiteSize = (380, 2800)
[INFO] CoreAreaLxLy = (20140, 22400)
[INFO] CoreAreaUxUy = (1680360, 1680000)
[INFO] NumInstances = 21392
[INFO] NumPlaceInstances = 18426
[INFO] NumFixedInstances = 2966
[INFO] NumDummyInstances = 0
[INFO] NumNets = 21032
[INFO] NumPins = 59025
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (1700260, 1701600)
[INFO] CoreAreaLxLy = (20140, 22400)
[INFO] CoreAreaUxUy = (1680360, 1680000)
[INFO] CoreArea = 2751980672000
[INFO] NonPlaceInstsArea = 3155824000
[INFO] PlaceInstsArea = 184237984000
[INFO] Util(%) = 6.702427
[INFO] StdInstsArea = 184237984000
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 9.40766e-05 HPWL: 2055551700
[InitialPlace]  Iter: 2 CG Error: 6.13227e-05 HPWL: 1573406637
[InitialPlace]  Iter: 3 CG Error: 4.61366e-05 HPWL: 1558483869
[InitialPlace]  Iter: 4 CG Error: 3.50621e-05 HPWL: 1539441037
[InitialPlace]  Iter: 5 CG Error: 2.49481e-06 HPWL: 1533589517
[INFO] FillerInit: NumGCells = 85894
[INFO] FillerInit: NumGNets = 21032
[INFO] FillerInit: NumGPins = 59025
[INFO] TargetDensity = 0.300000
[INFO] AveragePlaceInstArea = 9998805
[INFO] IdealBinArea = 33329348
[INFO] IdealBinCnt = 82569
[INFO] TotalBinArea = 2751980672000
[INFO] BinCnt = (256, 256)
[INFO] BinSize = (6486, 6475)
[INFO] NumBins = 65536
[NesterovSolve] Iter: 1 overflow: 0.963505 HPWL: 1419871020
[NesterovSolve] Iter: 10 overflow: 0.816161 HPWL: 1814183015
[NesterovSolve] Iter: 20 overflow: 0.803429 HPWL: 1766025678
[NesterovSolve] Iter: 30 overflow: 0.797274 HPWL: 1769386195
[NesterovSolve] Iter: 40 overflow: 0.795752 HPWL: 1763412967
[NesterovSolve] Iter: 50 overflow: 0.795315 HPWL: 1762737228
[NesterovSolve] Iter: 60 overflow: 0.795221 HPWL: 1762160440
[NesterovSolve] Iter: 70 overflow: 0.795573 HPWL: 1761999390
[NesterovSolve] Iter: 80 overflow: 0.795823 HPWL: 1761988992
[NesterovSolve] Iter: 90 overflow: 0.796156 HPWL: 1762065001
[NesterovSolve] Iter: 100 overflow: 0.79616 HPWL: 1762355857
[NesterovSolve] Iter: 110 overflow: 0.796008 HPWL: 1762502022
[NesterovSolve] Iter: 120 overflow: 0.795763 HPWL: 1762810688
[NesterovSolve] Iter: 130 overflow: 0.795452 HPWL: 1763402817
[NesterovSolve] Iter: 140 overflow: 0.794881 HPWL: 1764448629
[NesterovSolve] Iter: 150 overflow: 0.794087 HPWL: 1766434592
[NesterovSolve] Iter: 160 overflow: 0.792781 HPWL: 1769499142
[NesterovSolve] Iter: 170 overflow: 0.790413 HPWL: 1774028536
[NesterovSolve] Iter: 180 overflow: 0.787446 HPWL: 1781176208
[NesterovSolve] Iter: 190 overflow: 0.781903 HPWL: 1791570477
[NesterovSolve] Iter: 200 overflow: 0.773854 HPWL: 1803027216
[NesterovSolve] Iter: 210 overflow: 0.761658 HPWL: 1818037661
[NesterovSolve] Iter: 220 overflow: 0.746063 HPWL: 1827765410
[NesterovSolve] Iter: 230 overflow: 0.720665 HPWL: 1835018094
[NesterovSolve] Iter: 240 overflow: 0.69075 HPWL: 1848180481
[NesterovSolve] Iter: 250 overflow: 0.652511 HPWL: 1884601640
[NesterovSolve] Iter: 260 overflow: 0.615183 HPWL: 1902035485
[NesterovSolve] Iter: 270 overflow: 0.570578 HPWL: 1921197698
[NesterovSolve] Iter: 280 overflow: 0.525552 HPWL: 1943840730
[NesterovSolve] Iter: 290 overflow: 0.481713 HPWL: 1952233273
[NesterovSolve] Iter: 300 overflow: 0.465906 HPWL: 1948373256
[NesterovSolve] Iter: 310 overflow: 0.420875 HPWL: 1960660895
[NesterovSolve] Iter: 320 overflow: 0.388099 HPWL: 1961787861
[NesterovSolve] Iter: 330 overflow: 0.35254 HPWL: 1960484946
[NesterovSolve] Iter: 340 overflow: 0.327271 HPWL: 1956596977
[NesterovSolve] Iter: 350 overflow: 0.29797 HPWL: 1954685760
[NesterovSolve] Iter: 360 overflow: 0.273946 HPWL: 1952369229
[NesterovSolve] Iter: 370 overflow: 0.249655 HPWL: 1950605865
[NesterovSolve] Iter: 380 overflow: 0.224101 HPWL: 1949860309
[NesterovSolve] Iter: 390 overflow: 0.199229 HPWL: 1950348258
[NesterovSolve] Iter: 400 overflow: 0.177861 HPWL: 1950952318
[NesterovSolve] Iter: 410 overflow: 0.157597 HPWL: 1951768343
[NesterovSolve] Iter: 420 overflow: 0.139674 HPWL: 1952989006
[NesterovSolve] Iter: 430 overflow: 0.121866 HPWL: 1954568954
[NesterovSolve] Iter: 440 overflow: 0.107102 HPWL: 1956132144
[NesterovSolve] Finished with Overflow: 0.0999852
0:29.54elapsed 99%CPU 201212memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/resize.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_2_resizer.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_1_place_gp.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 21392 components and 100636 component-terminals.
Notice 0:     Created 5 special nets and 42784 connections.
Notice 0:     Created 21032 nets and 57852 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_1_place_gp.def

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _34448_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _35788_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _34448_/CK (DFF_X1)
   0.08    0.08 ^ _34448_/Q (DFF_X1)
   0.17    0.26 ^ _30335_/Z (BUF_X1)
   0.01    0.27 v _17452_/ZN (NOR2_X4)
   0.04    0.32 v _17454_/ZN (AND2_X4)
   0.03    0.35 ^ _17544_/ZN (NOR2_X4)
   0.01    0.36 v _17565_/ZN (INV_X2)
   0.03    0.39 v _17566_/ZN (AND3_X2)
   0.03    0.42 ^ _17572_/ZN (NOR2_X2)
   0.03    0.45 ^ _17578_/ZN (AND2_X4)
   0.03    0.48 ^ _17585_/ZN (AND2_X2)
   0.04    0.52 ^ _17597_/ZN (AND2_X2)
   0.03    0.55 ^ _17598_/ZN (AND2_X4)
   0.02    0.57 ^ _17599_/Z (BUF_X8)
   0.04    0.61 ^ _18829_/ZN (AND3_X4)
   0.04    0.64 ^ _21215_/ZN (AND2_X4)
   0.03    0.67 ^ _21304_/Z (BUF_X8)
   0.06    0.73 v _22227_/Z (MUX2_X1)
   0.04    0.77 v _22228_/ZN (OR2_X2)
   0.03    0.81 v _22229_/ZN (AND3_X2)
   0.04    0.84 v _22235_/ZN (OR2_X4)
   0.05    0.90 v _22236_/Z (MUX2_X2)
   0.05    0.95 v _22237_/Z (MUX2_X2)
   0.03    0.97 v _32395_/Z (BUF_X1)
   0.00    0.97 v _35788_/D (DFF_X1)
           0.97   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _35788_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -0.97   data arrival time
---------------------------------------------------------
          -0.01   slack (VIOLATED)

==========================================================================
report_tns
--------------------------------------------------------------------------
tns -0.03

==========================================================================
report_wns
--------------------------------------------------------------------------
wns -0.01

==========================================================================
report_design_area
--------------------------------------------------------------------------
Design area 27243 u^2 4% utilization.

==========================================================================
instance_count
--------------------------------------------------------------------------
21392

==========================================================================
pin_count
--------------------------------------------------------------------------
57852

Perform port buffering...
Inserted 1091 input buffers.
Inserted 81 output buffers.
Repair max cap...
Found 21 max capacitance violations.
Inserted 43 buffers in 21 nets.
Repair max slew...
Repair max fanout...
Perform resizing...
Warning: resize.tcl, 79 resize -dont_use is deprecated. Use the set_dont_use commands instead.
Resized 6150 instances.
Repair tie lo fanout...
Repair tie hi fanout...
Repair hold violations...
Inserted 0 hold buffers.

==========================================================================
report_floating_nets
--------------------------------------------------------------------------
Warning: found 1510 floatiing nets.

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _34447_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _35788_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _34447_/CK (DFF_X1)
   0.08    0.08 v _34447_/Q (DFF_X1)
   0.02    0.10 v _30333_/Z (CLKBUF_X1)
   0.04    0.14 v max_cap1211/Z (CLKBUF_X1)
   0.02    0.16 ^ _17451_/ZN (INV_X1)
   0.02    0.18 v _17452_/ZN (NOR2_X1)
   0.04    0.22 v _17454_/ZN (AND2_X1)
   0.05    0.27 ^ _17544_/ZN (NOR2_X1)
   0.01    0.29 v _17565_/ZN (INV_X1)
   0.03    0.32 v _17566_/ZN (AND3_X1)
   0.03    0.35 ^ _17572_/ZN (NOR2_X1)
   0.04    0.39 ^ _17578_/ZN (AND2_X1)
   0.03    0.42 ^ _17585_/ZN (AND2_X1)
   0.05    0.47 ^ _17597_/ZN (AND2_X1)
   0.04    0.51 ^ _17598_/ZN (AND2_X1)
   0.03    0.54 ^ _17599_/Z (BUF_X2)
   0.05    0.59 ^ _18829_/ZN (AND3_X1)
   0.05    0.64 ^ _21215_/ZN (AND2_X1)
   0.05    0.69 ^ _21304_/Z (BUF_X2)
   0.06    0.75 v _22227_/Z (MUX2_X1)
   0.04    0.79 v _22228_/ZN (OR2_X1)
   0.03    0.83 v _22229_/ZN (AND3_X1)
   0.04    0.87 v _22235_/ZN (OR2_X1)
   0.06    0.92 v _22236_/Z (MUX2_X1)
   0.06    0.98 v _22237_/Z (MUX2_X1)
   0.03    1.01 v _32395_/Z (CLKBUF_X1)
   0.00    1.01 v _35788_/D (DFF_X1)
           1.01   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _35788_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -1.01   data arrival time
---------------------------------------------------------
          -0.04   slack (VIOLATED)

==========================================================================
report_tns
--------------------------------------------------------------------------
tns -0.32

==========================================================================
report_wns
--------------------------------------------------------------------------
wns -0.04

==========================================================================
report_design_area
--------------------------------------------------------------------------
Design area 28283 u^2 4% utilization.

==========================================================================
instance_count
--------------------------------------------------------------------------
22607

==========================================================================
pin_count
--------------------------------------------------------------------------
60282

0:11.90elapsed 99%CPU 173608memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/detail_place.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_3_opendp.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_2_place_resized.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 22607 components and 105496 component-terminals.
Notice 0:     Created 5 special nets and 45214 connections.
Notice 0:     Created 22247 nets and 60282 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_2_place_resized.def
Design Stats
--------------------------------
total instances         22607
multi row instances         0
fixed instances          2966
nets                    22252
design area          687995.2 u^2
fixed area              789.0 u^2
movable area          27494.3 u^2
utilization                 4 %
utilization padded          6 %
rows                      592
row height                1.4 u

Placement Analysis
--------------------------------
total displacement    18612.4 u
average displacement      0.8 u
max displacement          6.6 u
original HPWL        984736.1 u
legalized HPWL       990222.5 u
delta HPWL                  1 %

0:01.44elapsed 100%CPU 224160memKB
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_3_place_dp.def results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.def
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.sdc results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.sdc
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/cts.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_1_cts.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 22607 components and 105496 component-terminals.
Notice 0:     Created 5 special nets and 45214 connections.
Notice 0:     Created 22247 nets and 60282 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.def

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _34447_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _35788_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _34447_/CK (DFF_X1)
   0.08    0.08 v _34447_/Q (DFF_X1)
   0.03    0.11 v _30333_/Z (CLKBUF_X1)
   0.04    0.15 v max_cap1211/Z (CLKBUF_X1)
   0.02    0.17 ^ _17451_/ZN (INV_X1)
   0.02    0.19 v _17452_/ZN (NOR2_X1)
   0.05    0.24 v _17454_/ZN (AND2_X1)
   0.06    0.30 ^ _17544_/ZN (NOR2_X1)
   0.02    0.32 v _17565_/ZN (INV_X1)
   0.03    0.35 v _17566_/ZN (AND3_X1)
   0.04    0.39 ^ _17572_/ZN (NOR2_X1)
   0.05    0.44 ^ _17578_/ZN (AND2_X1)
   0.04    0.47 ^ _17585_/ZN (AND2_X1)
   0.06    0.53 ^ _17597_/ZN (AND2_X1)
   0.04    0.57 ^ _17598_/ZN (AND2_X1)
   0.04    0.61 ^ _17599_/Z (BUF_X2)
   0.05    0.67 ^ _18829_/ZN (AND3_X1)
   0.06    0.73 ^ _21215_/ZN (AND2_X1)
   0.05    0.78 ^ _21304_/Z (BUF_X2)
   0.06    0.84 v _22227_/Z (MUX2_X1)
   0.04    0.88 v _22228_/ZN (OR2_X1)
   0.03    0.91 v _22229_/ZN (AND3_X1)
   0.04    0.96 v _22235_/ZN (OR2_X1)
   0.06    1.01 v _22236_/Z (MUX2_X1)
   0.06    1.07 v _22237_/Z (MUX2_X1)
   0.03    1.10 v _32395_/Z (CLKBUF_X1)
   0.00    1.10 v _35788_/D (DFF_X1)
           1.10   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _35788_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -1.10   data arrival time
---------------------------------------------------------
          -0.14   slack (VIOLATED)

 *****************
 * TritonCTS 2.0 *
 *****************
 *****************************
 *  Import characterization  *
 *****************************
 Reading LUT file "./platforms/nangate45/tritonCTS/lut.txt"
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          52           1          24
    [WARNING] 180 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 4994
    Num keys in characterization LUT: 1677
    Actual min input cap: 8
 Reading solution list file "./platforms/nangate45/tritonCTS/sol_list.txt"
 **********************
 *  Find clock roots  *
 **********************
 User did not specify clock roots.
 Using OpenSTA to find clock roots.
 Looking for clock sources...
    Clock names: clock 
 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Number of user-input clocks: 1 ( "clock" )
 Looking for clock nets in the design
 Net "clock" found
clock
 ****************************
 *  Check characterization  *
 ****************************
    The chacterization used 1 buffer(s) types. All of them are in the loaded DB.
 ***********************
 *  Build clock trees  *
 ***********************
 Generating H-Tree topology for net clock...
    Tot. number of sinks: 1514
 Wire segment unit: 20000 dbu (10 um)
 Original sink region: [(405270, 452030), (1264070, 1289570)]
 Normalized sink region: [(20.2635, 22.6015), (63.2035, 64.4785)]
    Width:  42.94
    Height: 41.877
 Level 1
    Direction: Horizontal
    # sinks per sub-region: 757
    Sub-region size: 21.47 X 41.877
    Segment length (rounded): 10
    Key: 3192 outSlew: 1 load: 1 length: 8 isBuffered: 1
    Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
 Level 2
    Direction: Vertical
    # sinks per sub-region: 379
    Sub-region size: 21.47 X 20.9385
    Segment length (rounded): 10
    Key: 3206 outSlew: 1 load: 1 length: 8 isBuffered: 1
    Key: 436 outSlew: 1 load: 1 length: 2 isBuffered: 1
 Level 3
    Direction: Horizontal
    # sinks per sub-region: 190
    Sub-region size: 10.735 X 20.9385
    Segment length (rounded): 6
    Key: 2280 outSlew: 22 load: 1 length: 6 isBuffered: 1
 Level 4
    Direction: Vertical
    # sinks per sub-region: 95
    Sub-region size: 10.735 X 10.4692
    Segment length (rounded): 6
    Key: 1990 outSlew: 2 load: 1 length: 6 isBuffered: 1
 Level 5
    Direction: Horizontal
    # sinks per sub-region: 48
    Sub-region size: 5.3675 X 10.4692
    Segment length (rounded): 2
    Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
 Level 6
    Direction: Vertical
    # sinks per sub-region: 24
    Sub-region size: 5.3675 X 5.23462
    Segment length (rounded): 2
    Key: 34 outSlew: 3 load: 1 length: 2 isBuffered: 0
 [WARNING] Creating fake entries in the LUT.
 Level 7
    Direction: Horizontal
    # sinks per sub-region: 12
    Sub-region size: 2.68375 X 5.23462
    Segment length (rounded): 1
    Key: 5031 outSlew: 12 load: 1 length: 1 isBuffered: 1
 Stop criterion found. Max number of sinks is (15)
 Building clock sub nets...
 Number of sinks covered: 1514
 Clock topology of net "clock" done.
 ****************
 * Post CTS opt *
 ****************
 Avg. source sink dist: 56566.9 dbu.
 Num outlier sinks: 7
 ********************
 * Write data to DB *
 ********************
 Writing clock net "clock" to DB
    Created 170 clock buffers.
    Created 170 clock nets.
 ... End of TritonCTS execution.
Design Stats
--------------------------------
total instances         22777
multi row instances         0
fixed instances          2966
nets                    22422
design area          687995.2 u^2
fixed area              789.0 u^2
movable area          27638.5 u^2
utilization                 4 %
utilization padded          6 %
rows                      592
row height                1.4 u

Placement Analysis
--------------------------------
total displacement      161.6 u
average displacement      0.0 u
max displacement          2.6 u
original HPWL        1004050.8 u
legalized HPWL       1004064.7 u
delta HPWL                  0 %

0:03.31elapsed 100%CPU 238972memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/fillcell.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_2_cts_fillcell.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_1_cts.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 22777 components and 106176 component-terminals.
Notice 0:     Created 5 special nets and 45554 connections.
Notice 0:     Created 22417 nets and 60622 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_1_cts.def
Placed 132710 filler instances.
0:01.69elapsed 99%CPU 370676memKB
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_2_cts_fillcell.def results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_cts.def
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/global_route.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/5_1_fastroute.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_cts.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:       Created 100000 Insts
Notice 0:     Created 1173 pins.
Notice 0:     Created 155487 components and 371596 component-terminals.
Notice 0:     Created 5 special nets and 310974 connections.
Notice 0:     Created 22417 nets and 60622 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_cts.def
*** buffer overflow detected ***: openroad terminated
Command terminated by signal 6
0:06.82elapsed 98%CPU 387316memKB
Makefile:326: recipe for target 'results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/route.guide' failed
make: *** [results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/route.guide] Error 134
eder-matheus commented 4 years ago

I see. Sorry to ask for it again, but can you point me how do I reproduce this issue on my side, step by step? (e.g., what repositories I should clone, how should I the directories, etc...)

tamimcse commented 4 years ago

This is how I did it:

  1. Installed OpenROAD openroad branch
  2. Also installed Yosys and TritonRoute from source code. Installing Yosys via apt-get doesn't work.
  3. Cloned OpenROAD-Flow openroad branch
  4. I went to OpenROAD-flow/flow/designs/src. Created a folder same sail. Entered inside sail. Cloned https://github.com/tamimcse/test5 there. This will fetch the makefile, sdc and verilog file.
  5. Then opened OpenROAD-flow/flow/Makefile. Set DESIGN_CONFIG ?= ./designs/src/sail/sail.mk. It points to gcd.mk by default, so we needed to update it.
  6. Now execute source setup_env.sh in OpenROAD-Flow
  7. Then execute make in OpenROAD-Flow/flow The make will execute OpenROAD flow on our files.
eder-matheus commented 4 years ago

Thank you very much! I will try it on my end and let you know when I have updates

maliberty commented 3 years ago

@eder-matheus is this resolved?

vijayank88 commented 1 year ago

Required repo link missing to reproduce the issue. Try with latest OpenROAD flow, please re-open with test case again, if there is crash still.