maliberty
commented
3 days ago @jeffng-or if you zoom in the leafs on the skewed side you can select them to see what instances they are.
Open jeffng-or opened 3 days ago
maliberty
commented
3 days ago @jeffng-or if you zoom in the leafs on the skewed side you can select them to see what instances they are.
arthurjolo
commented
3 days ago @jeffng-or Do you know if there are any clock gaters on this design? Clock gaters have some issues currently.
jeffng-or
commented
3 days ago @jeffng-or Do you know if there are any clock gaters on this design? Clock gaters have some issues currently.
AFAIK, no clock gaters. The only cells used in the clock tree look to be bufs or invs:
(BUFx10_ASAP7_75t_R) (BUFx12_ASAP7_75t_R) (BUFx12f_ASAP7_75t_R) (BUFx16f_ASAP7_75t_R) (BUFx24_ASAP7_75t_R) (BUFx4f_ASAP7_75t_R) (BUFx6f_ASAP7_75t_R) (CKINVDCx10_ASAP7_75t_R) (CKINVDCx11_ASAP7_75t_R) (CKINVDCx12_ASAP7_75t_R) (CKINVDCx14_ASAP7_75t_R) (CKINVDCx16_ASAP7_75t_R) (CKINVDCx20_ASAP7_75t_R) (CKINVDCx5p33_ASAP7_75t_R) (CKINVDCx6p67_ASAP7_75t_R) (CKINVDCx8_ASAP7_75t_R) (CKINVDCx9p33_ASAP7_75t_R) (INVx13_ASAP7_75t_R) (INVx3_ASAP7_75t_R) (INVx5_ASAP7_75t_R) (INVx6_ASAP7_75t_R) (INVx8_ASAP7_75t_R) (INVxp33_ASAP7_75t_R) (INVxp67_ASAP7_75t_R)
jeffng-or
commented
3 days ago @jeffng-or if you zoom in the leafs on the skewed side you can select them to see what instances they are.
The far right branch connects to one macro: dcache/data/array_1_0_ext/R0_clk.
The other long branch nearer to the middle of the clock tree is clknet_leaf_402_clock_regs, which connects to:
maliberty
commented
3 days ago It branches off the tree very high up. If you look at where it branches do you see a gate?
jeffng-or
commented
3 days ago It branches off the tree very high up. If you look at where it branches do you see a gate?
I don't think so. I checked the connections at the colored dots in the clock tree:
In case you want to look at the clock tree in more detail, I have the output from a clock tree connectivity dumper that I wrote (no guarantee that it's totally correct). The output is a text file which can be found in: https://drive.google.com/file/d/1bL4rkNu9erDrZYoNKofA7MbXbJbnxByT/view?usp=sharing
maliberty
commented
3 days ago @arthurjolo is this due to splitting macros from std cells?
arthurjolo
commented
2 days ago I am going to open the design and take a close look on it, but I don't think this is due to the splitting of macros from std cells. On the macros branch Jeff mentioned that there are delay buffer so the average arrival time on the macro branch was smaller then on the std cells, so the other macros seem to have a better arrival time. I believe that CTS did a poor job connecting to dcache/data/array_1_0_ext/R0_clk, I am going to try to understand why.
arthurjolo
commented
2 days ago One thing that I noticed from Jeff's dump is that on the array_1_0_ext/R0_clk path there are 7 wire buffers between the leaf clk buffer and the CK pin, while on other leafs there are 3 or less buffers.
Describe the bug
For megaboom v6, I upped the clock frequency to 833 MHz and the resulting clock tree appears to be unbalanced (see the branch of the tree on the far right in the viewer) and with significant skew:
Tom mentioned that sometimes the clock tree will be unbalanced when connecting to macros, so I'd like to get some feedback on whether that's the case here. Note that prior versions of BoomTile with a slower clock generated a balanced clock tree with not as much skew.
Expected Behavior
Balanced clock tree with minimal skew
Environment
To Reproduce
I kept 3_place.odb in the tarball in case it's helpful.
Relevant log output
No response
Screenshots
No response
Additional Context
No response