Closed gadfort closed 4 weeks ago
A more reduced version of the test case is at https://drive.google.com/file/d/1uqTUyRmjeM3Qiv1uoAYdkEIKdR9ZW2bA/view?usp=sharing
I believe the problem originates with
void Resizer::removeBuffers(sta::InstanceSeq insts, bool recordJournal)
{
initBlock();
// Disable incremental timing.
graph_delay_calc_->delaysInvalid();
search_->arrivalsInvalid();
When the last line is commented out the problem disappears. I see the arrivals_ in the Graph are cleared:
Search::arrivalsInvalid() -> Search::deletePaths() -> graph->clearArrivals(); -> arrivals.clear();
but I can find no code that clears the Vertex's arrivals. This leads to an invalid access of the arrivals table.
@jjcherry56 please confirm if this is a correct analysis of the problem. The OR test case is provided above.
@maliberty @gadfort is there a way to make this testcase read a netlist and then fail versus running the flow?
@tspyrou the testcase @maliberty posted has already been pruned down. Matt tried to do a deltaDebug thing, but I don't know if that yielded anything. If i revert https://github.com/The-OpenROAD-Project/OpenSTA/commit/be563b67097c5d3f5b7bda7f63a0e2926424355d out of the STA build, the segfault goes away.
@jjcherry56 fyi above
delta debug didn't make it much smaller
The issue for debugging it is that in order to build openroad on macos I have to comment out the rtl macro placer and this test case uses it. What would help is to have a db+command file that starts after the rtl placer.
@parallaxsw Are you using the test case from "A more reduced version of the test case is at" above? I don't think it uses mpl2
@gadfort would confirm? The sc scripts are hard to read.
@maliberty yes, the reduced case, has the macro placement removed.
I can run the reduced case.
@parallaxsw ETA to fix this? I'm wondering if I need to revert the sta update in OR to unblock @gadfort or if this can be fixed quickly.
The failure is because the vss/vssio/vdd/vddio ports are bidirectional when check_setup is called and then change to gnd/power when report_checks "necessary to trigger the failure". The distinction is important to opensta (2 vertices versus no vertices). It is possible to compensate in opensta but I think openroad should be able to correctly identify power and ground ports or delete/add them when changing the direction.
@parallaxsw Please give an example of such a port that changes type. dbNetwork::direction either uses Liberty or LEF in
PortDirection* dbNetwork::dbToSta(const dbSigType& sig_type,
const dbIoType& io_type) const
so its hard to see how the type changes.
There are some pad cells that have:
MACRO sky130_ef_io__com_bus_slice_1um
PIN VSSA
DIRECTION INOUT ;
USE GROUND ;
But ground should take precedence over inout.
nvm - I see it is a top level bterm not an iterm that is bidir
There is no way to know from the Verilog. OR only learns about this during pad frame generation. If I add to the sdc:
set_logic_one vdd
set_logic_one vddio
set_logic_zero vss
set_logic_zero vssio
the problem goes away.
To prevent crashes OR will reset the graph on any sigtype change as sta can't handle it.
Describe the bug
During
report_checks
OpenROAD segfaults.Expected Behavior
No segfault
Environment
To Reproduce
See updated test case below (previously https://drive.google.com/file/d/1M11jBLsGJc24GXY1dFDw3XNuZuDqXNYc/view?usp=sharing)
Relevant log output
Screenshots
No response
Additional Context
No response