false hold violations and false negatives on setup violations in floorplan due to mixing propagated clock in macros and ideal clock of top level

[oharboe]

Description

In megaboom there are macros that have a non-trivial network clock insertion latency internally. This causes the floorplan with 0 clock network insertion latency at the top level to believe that there are hold violations.

megaboom uses HOLD_SLACK_MARGIN=-300, so no hold cells are inserted in this case.

In the past, I have seen megaboom gnaw on the problem of how to get rid of these hold violations for a very long time.

Doesn't this case false negatives on setup violations too?

Suggested Solution

Unsure. Modify timing to set network clock insertion latency of macros to 0 instead of using a mix of ideal and propagated clock.

Additional Context

No response

[maliberty]

My plan has been to turn off hold fixing in floorplan which should make this moot.

[oharboe]

My plan has been to turn off hold fixing in floorplan which should make this moot.

What about false setup violations?

If the toplevel has 0 clock latency(ideal clock) and the macro has propagated clock and significant clock insertion latency then there can easily be a false setup violation during floorplan timing repair.

[maliberty]

Whether it helps or hurts depends if it is on the launching or capturing end of the path. Its a good question for @tspyrou as to what is the normal sta handling here.

[oharboe]

Whether it helps or hurts depends if it is on the launching or capturing end of the path. Its a good question for @tspyrou as to what is the normal sta handling here.

I see. I didn't think about the case where a signal is captured inside a macro, but yes: there you get false setup non-violations of course.