There's some doubt about second clock rise edge delay

[HerrySong]

Hi, I use commands "create_clock -name clk2 -period 4 -waveform {0.5 1.5 2.5 3.5} [get_ports clk] set_propagated_clock [all_clocks] report_checks -path_delay max -fields capacitance -from state_reg0/CP -to fpga2dsp_date_shift_reg6/D -digits 6 " to check a max path, I think the second clk2's rise edge time is 2.5, means data required time should start from 2.5, but in the OpenSTA report，data required time start from 4.5, I don't know where is wrong

[jjcherry56]

I generally refuse to even respond to issues that do not contain a testcase because english is a poor substitute for describing a problem.

However, in this case the problem appears to be pretty obvious. The rising edge at 4.5ns is the first rising edge in the clock period following the source clock (because the period is 4). The underlying problem is that the clock period is really 2 (just look at the waveform) and the waveform should only have 2 edge times, not 4.