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The-OpenROAD-Project / OpenSTA

OpenSTA engine
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Verilog assign and SPEF annotation #113

Closed shalan closed 1 year ago

shalan commented 1 year ago

Does OpenSTA handle assign statements in the netlist while loading SPEF files?

Loading a SPEF file to annotate a netlist that has assign statements emits warnings about nets being not connected. For example: 

Warning: ~/spef/xyz-nom-t.spef line 6060, *2803 not connected to net gpio_clock_1_shifted\[0\].

The net represented by *2803 is connected to gpio_clock_1_shifted\[0\] using an assign statement in the netlist.

I confirmed that the annotation did not take place on these nets. OpenSTA does report any delay for this net.

maliberty commented 1 year ago

You should provide a test case

jjcherry56 commented 1 year ago

Short of providing a testcase can you at least describe what nets the assign connects? Input? Outputs? Hierarchical module ports? The probability of fixing the problem you have is much smaller if I have to guess what the netlist looks like.

tspyrou commented 1 year ago

@shalan is this a hierarchical spef flow? If not it would be good to get the testcase so it can be fixed.

jjcherry56 commented 1 year ago

I tried to reproduce this with the attached verilog/spef but it worked as expected. Maybe you can modify the attached test case to reproduce your issue.

sta113.zip