Closed taylor-bsg closed 2 years ago
Not really. You want the delay calculation for gate delays in the clock network but not the slews? It is a strange request. Seem like you should be using ideal clocks with set_clock_latency and set_clock_transition.
Thanks for your reply. What I mean is, let's say you have a clock tree and you have parasitics for it. The clock tree still has a source, for which we want to specify a slew; what is the mechanism for specifying this?
set_input_transition
Actually I am saying, I want it to time the clock tree and everything with slews etc, but the clock input pin itself has a slew.
On Thu, Aug 25, 2022 at 11:36 AM James Cherry @.***> wrote:
Not really. You want the delay calculation for gate delays in the clock network but not the slews? It is a strange request. Seem like you should be using ideal clocks with set_clock_latency and set_clock_transition.
— Reply to this email directly, view it on GitHub https://github.com/The-OpenROAD-Project/OpenSTA/issues/117#issuecomment-1227627276, or unsubscribe https://github.com/notifications/unsubscribe-auth/AEFG5AG33QBTXWRQMAR2COTV264LBANCNFSM57RS42NQ . You are receiving this because you authored the thread.Message ID: @.***>
Okay great, I did not know this could be applied to a clock signal as well.
M
On Fri, Aug 26, 2022 at 7:13 AM James Cherry @.***> wrote:
Closed #117 https://github.com/The-OpenROAD-Project/OpenSTA/issues/117 as completed.
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Is this possible? I checked the docs and did not see any mention of it.
Thanks!