Closed Fraserbc closed 1 year ago
@Fraserbc Refer following doc: https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf
I've just read through it again and can't see anything showing how to create a generated clock using a net as a source. Is there any workaround?
@Fraserbc
Can you attach test case with .sdc
file you're facing the issue?
Here's an example of what I'm trying to do
# Create the first clock
create_generated_clock -name CLK1 -source [get_ports clk_in] \
-divide_by 2 [get_nets CLK_DIV_2]
create_generated_clock -name CLK2 -source [get_nets CLK_DIV_2] \
-divide_by 2 [get_nets CLK_DIV_4]
I want to be able to create a generated clock with the master being another generated clock, without the source being a pin.
@Fraserbc Can you share source verilog file?
[get_nets CLK_DIV_2]
unable to resolve during the process i think.
By providing pin list it will work. Example:
create_generated_clock -name gclk1 -source clk1 -divide_by 4 r1/Q
Nets are not supported for generated clock sources. It is actually pretty strange and counter to the documentation (that I wrote) that nets are supported for the clock root. The net is converted to the driver pin(s) of the net. The SDC to do the equivalent is [get_pins -of_object [get_net CLK_DIV_2] -filter "direction == output"]
@jjcherry56 Thanks so much! That's exactly what I was looking for. By any chance do you have any good places to learn about SDC constraints, specifically things like that [get_pins -of_object [get_net CLK_DIV_2] -filter "direction == output"]
?
Hi,
I have two issues with
create_generated_clock
. The first is when trying to use themaster_clock
argument without providingsource
is errors out withmissing -source argument.
, but according to this it should work.My second issue is that it requires
source
to be a pin or a port as it errors withmaster_pin type 'Net' is not a pin or port.
, not allowing nets to be used.