write_verilog missing wire dcls for unconnected concatenation

[antonblanchard]

OpenSTA is creating implicit wires on unconnected buses. An example is attached, which creates the following Verilog:

module module1 ();

 module2 m (.A0({_NC1,
    _NC2}));
endmodule

It's a minor issue, a result of the gate level test using default_nettype none somewhere and fixed by adding default_nettype wire. I did notice OpenSTA emits wire statements elsewhere, so hopefully it could do the same for this case.

Testcase: sta-implicit-wire.tar.gz

[jjcherry56]

ya, a bit tricky because those net names aren't known until deep into the write...

[jjcherry56]

fixed in 46c6838