reporting results of wire load model, model generation.

[andyfox-rushc]

1. When issuing a report_checks command I see the cell delays correctly reported (I checked them) but don't see the wire load estimates per pin. Is this supported in Open Sta ? (or perhaps I am missing something : I was expecting to see a wire load contribution on the input pins).

Example: 0.00000 0.00000 clock clk (rise edge) 0.00000 0.00000 clock network delay (ideal) 0.00000 0.00000 ^ sa23_reg1/CK (DFF_X1) 0.11288 0.11288 ^ sa23_reg1/Q (DFF_X1) 0.01537 0.12824 v us23/U8/ZN (INV_X1) <-- correct cell delay. But no wire delay reported on pin A1. 0.02344 0.15168 ^ us23/U9/ZN (NAND2_X1)

in another tool... the same cell delay AND a delay on the input pin A (from wireload) is reported eg: us23/U8/A (INV_X1) 0.01889 0.13178 r <- input wire delay us23/U8/ZN (INV_X1) 0.01548 0.14726 f <- cell delay

2. When issuing a write_timing_model command for the inverter cell in the above path I see a bad model (a sequential model) generated. Is this pilot error or a real bug. Here is part of the INV_X1 model generated: cell ("INV_X1") { pin("clk") { <-- weird, why is there a clk in an inverter model ??. direction : input; capacitance : 731.4056; }

Here is the script to reproduce (I also included a report_dcalc to manually check that only the cell delay is included in the report).

read_liberty NangateOpenCellLibrary_typical.lib read_verilog aes_cipher_top.synth.final.v link_design aes_cipher_top set_wire_load_mode enclosed set_wire_load_model -name 5K_hvratio_1_1 -library NangateOpenCellLibrary read_sdc sdc.sdc report_checks -format full -digits 5

looks ok shows cell delay and slews. But does not show wire load

report_dcalc -from us23/U8/A -to us23/U8/ZN -digits 5

Weird.

write_timing_model -library_name NangateOpenCellLibrary_typical -cell_name INV_X1 inv_x1.model

Here are the test files (NangateOpenCellLibrary_typical can be found in OpenRoad). inv_x1.model shows what I see.

sta_cmds.txt

aes_cipher_top.synth.final.v.gz sdc.sdc.gz

inv_x1.model.gz

[jjcherry56]

Use report_checks -fields {input_pin} to see arrivals/delays at input pins. You can't write a timing model for an inverter in the design. It writes a model for THE DESIGN. Those args are for what to call it in the liberty file it writes.