Write verilog doesn't reflect interconnected power ports

[smunaut]

You can have multiple power / ground ports connected to each other in the database and this will not be reflected in the written verilog. This results in LVS errors later in the flow because the powered netlist written by openroad doesn't math the extracted spice netlist.

I applied this path to fix it locally :

diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
index e3362da..51cf317 100644
--- a/verilog/VerilogWriter.cc
+++ b/verilog/VerilogWriter.cc
@@ -214,9 +214,9 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
   else if (dir == PortDirection::bidirect())
     return "inout";
   else if (dir == PortDirection::power())
-    return "input";
+    return "inout";
   else if (dir == PortDirection::ground())
-    return "input";
+    return "inout";
   else if (dir == PortDirection::internal())
     return nullptr;
   else {
@@ -412,7 +412,7 @@ VerilogWriter::writeAssigns(Instance *inst)
     Net *net = network_->net(term);
     Port *port = network_->port(pin);
     if (port
-        && network_->direction(port)->isAnyOutput()
+        && (network_->direction(port)->isAnyOutput() || network_->direction(port)->isPowerGround())
         && !stringEqual(network_->name(port), network_->name(net))) {
       // Port name is different from net name.
       string port_vname = netVerilogName(network_->name(port),

[maliberty]

Its best to file this against the upstream https://github.com/parallaxsw/OpenSTA

[smunaut]

My bad, I thought this was upstream ... I wasn't aware it was a clone/fork since it's not shown as such on github.

[maliberty]

Sorry, it isn't obvious.

[smunaut]

It's been fixed upstream FWIW