Setup slack is zero when time borrowing, pessimistic for latches

[toivoh]

For latches, OpenSTA considers the normal setup timing case to be that input data should arrive before the event when latch becomes transparent, and that the output data becomes valid triggered by this event. Only if data does not arrive before the latch becomes transparent, time is borrowed from the setup time for the paths starting at the data output, borrowing only as much time as needed to give the input path a setup slack of zero. This causes the setup slack to (sometimes severely) underestimate the setup timing margin, especially when time borrowing, and the latter case causes the OpenLane 2 flow to fail, since it considers a setup slack of zero to be a timing violation.

Setup slack should be a measure of the margin for timing degradation before setup timing constraints start to fail; ideally how much the clock period can be reduced before this happens. From this point of view latches should not borrow as little setup time as needed to reach zero slack. Ideally, they they should borrow so much time that the setup slack over all paths involving the latch is maximized. I realize that implementing such an optimization most likely amounts to a major effort that would not be motivated.

My suggestion is instead to add an option for target minimum setup time for timing paths ending at the D input of latches. If the setup time up to the event when the latch becomes transparent does not reach the target setup time, time borrowing is invoked to try to reach the target time (not borrowing more than available, of course). This would allow the user to find a suitable timing margin to trade off setup slack coming into and out of latches for a given design.

Example: The following module (using the sky130 pdk) causes time borrowing and a setup slack of zero:

module top (
        input wire clk,
        input wire d_in,
        output wire d_out
    );

    reg r_in, r_out;
    wire q;

    sky130_fd_sc_hd__dlxtp_1 latch( .GATE(clk), .D(r_in), .Q(q));

    always @(posedge clk) begin
        r_out <= q;
        r_in <= d_in;
    end
    assign d_out = r_out;
endmodule

[toivoh]

The target minimum setup time option for latches could be given as a percentage of the clock period and/or be possible to specify per clock, to allow better behavior for designs with multiple clocks.

[maliberty]

Issues or PRs should be filed with https://github.com/parallaxsw/OpenSTA if still relevant. This is effectively a fork (though not strictly for historical reasons).