errors with busses

[thesourcerer8]

When reading a verilog file with busses, I get errors like this: Error: synthesis/raven_spi.rtlbb.v, line 8 syntax error, unexpected ';', expecting '='.

[thesourcerer8]

Example file: http://www.futureware.at/~philipp/workshop/raven_spi.rtlbb.v

[jjcherry56]

foo[1] is not legal as a verilog port. You either have to escape the bus bits or group them ('foo' is the port and 'output [3:0] foo;' is the declaration). See the verilog LRM for syntax.