Unable to understand multi-assignment statements that uses '{'

[MohitHirpara]

Hi,

I am unable to read a verilog that has "{" used for multi-assignment e.g.:

assign { 5865[8:2], 5865[0] } = { 5861[8:2], 5861[0] };

Errors while using read_verilog :

% read_verilog netlist.v
Error: netlist.v, line 7619 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39379 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39380 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39383 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39587 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39612 syntax error, unexpected '{', expecting ID.

Can you please help me figure out if I am doing some mistake or this is actually a bug ? Thanks in Advance

[jjcherry56]

this is a duplicate of issue 31