taking divider delay into account with generated_clocks

[quentinw91]

Hi, I have a module with clock division inside, and i want to specify the output delays wrt the source clock instead of the generated one.

The sdc file is the following:

create_clock [get_ports CLK]  -name CLK  -period 2

create_generated_clock -name CLK_DIV -source CLK -divide_by 2 _5_/Q

set_input_delay -clock CLK  -max 0.5  [get_ports DATA_IN]
set_input_delay -clock CLK  -min 0  [get_ports DATA_IN]

#DATA1_OUT is starting from CLK
set_output_delay -clock CLK  -max 1  [get_ports DATA1_OUT]
set_output_delay -clock CLK  -min 0  [get_ports DATA1_OUT]

#DATA2_OUT is actually starting from CLK_DIV internally, but i want to specify the delay wrt source CLK
set_output_delay -clock CLK  -max 1  [get_ports DATA2_OUT]
set_output_delay -clock CLK  -min 0  [get_ports DATA2_OUT]

I then have the following report_checks:

[...]
Startpoint: _3_ (rising edge-triggered flip-flop clocked by CLK_DIV)
Endpoint: DATA2_OUT (output port clocked by CLK)
Path Group: CLK
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock CLK_DIV (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _3_/CK (DFFR_X1)
   0.10    0.10 ^ _3_/Q (DFFR_X1)
   0.00    0.10 ^ DATA2_OUT (out)
           0.10   data arrival time

   2.00    2.00   clock CLK (rise edge)
   0.00    2.00   clock network delay (ideal)
   0.00    2.00   clock reconvergence pessimism
  -1.00    1.00   output external delay
           1.00   data required time
---------------------------------------------------------
           1.00   data required time
          -0.10   data arrival time
---------------------------------------------------------
           0.90   slack (MET)

So OpenSTA looks to understand that the path is starting from a flip-flop clocked by CLK_DIV, but that i want to calculate the delay wrt to CLK. But the delay between CLK and CLK_DIV is not considered (so the DFF _5_ clock_to_Q delay). How can i have it taken into account in the path check ?

If you need a test case, i ran this using nangate45 library and openroad-flow (at master branch commit 660fdb4): testcase_genclock.zip

Thank you

[jjcherry56]

you have to use propagated for the clocks to have delay. you are using ideal clocks.

On Fri, Jul 10, 2020 at 4:58 AM quentinw91 notifications@github.com wrote:

Hi, I have a module with clock division inside, and i want to specify the output delays wrt the source clock instead of the generated one.

The sdc file is the following:

create_clock [get_ports CLK] -name CLK -period 2

create_generated_clock -name CLK_DIV -source CLK -divide_by 2 5/Q

set_input_delay -clock CLK -max 0.5 [get_ports DATA_IN] set_input_delay -clock CLK -min 0 [get_ports DATA_IN]

DATA1_OUT is starting from CLK

set_output_delay -clock CLK -max 1 [get_ports DATA1_OUT] set_output_delay -clock CLK -min 0 [get_ports DATA1_OUT]

DATA2_OUT is actually starting from CLK_DIV internally, but i want to specify the delay wrt source CLK

set_output_delay -clock CLK -max 1 [get_ports DATA2_OUT] set_output_delay -clock CLK -min 0 [get_ports DATA2_OUT]

I then have the following report_checks:

[...] Startpoint: 3 (rising edge-triggered flip-flop clocked by CLK_DIV) Endpoint: DATA2_OUT (output port clocked by CLK) Path Group: CLK Path Type: max

Delay Time Description

0.00 0.00 clock CLK_DIV (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ 3/CK (DFFR_X1) 0.10 0.10 ^ 3/Q (DFFR_X1) 0.00 0.10 ^ DATA2_OUT (out) 0.10 data arrival time

2.00 2.00 clock CLK (rise edge) 0.00 2.00 clock network delay (ideal) 0.00 2.00 clock reconvergence pessimism -1.00 1.00 output external delay 1.00 data required time

       1.00   data required time
      -0.10   data arrival time

---

       0.90   slack (MET)

So OpenSTA looks to understand that the path is starting from a flip-flop clocked by CLK_DIV, but that i want to calculate the delay wrt to CLK. But the delay between CLK and CLK_DIV is not considered (so the DFF 5 clock_to_Q delay). How can i have it taken into account in the path check ?

If you need a test case, i ran this using nangate45 library and openroad-flow (at master branch commit 660fdb4): testcase_genclock.zip https://github.com/The-OpenROAD-Project/OpenSTA/files/4902927/testcase_genclock.zip

Thank you

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