constrained output with reference pin gets marked as unconstrained

Hi, I am trying to synthesize a data and clock recovery module, and i am getting trouble constraining the design. Simplified testcase (ran with sta in standalone, rev 09524cb) : 20200918.zip

I am defining the constraints like this:

create_clock -name clk -period 10 {clk}

create_generated_clock -name clk_gen -source clk -divide_by 2 r2/Q

set_propagated_clock [all_clocks]

set_input_delay -clock clk -min 0.1 {in1 in2}
set_input_delay -clock clk -max 6 {in1 in2}

#constraint clk_out wrt to clk
set_output_delay -clock clk -max 8  [get_ports clk_out]
set_output_delay -clock clk -min 0  [get_ports clk_out]
set_load -pin_load -min 0.005 [get_ports clk_out]
set_load -pin_load -max 0.1   [get_ports clk_out]

#constraint data_out wrt to clk_out
set_output_delay -reference_pin [get_ports clk_out]  -max 7    [get_ports data_out]
set_output_delay -reference_pin [get_ports clk_out]  -min 0.05 [get_ports data_out]
set_load -pin_load -min 0.005 [get_ports data_out]
set_load -pin_load -max 0.1   [get_ports data_out]

I am getting a warning saying data_out is unconstrained

check_setup -unconstrained
Warning: There is 1 unconstrained endpoint.
  data_out

But the timing path looks to be correctly calculated in relation with clk_out:

Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: data_out (output port clocked by clk_gen)
Path Group: clk_gen
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
----------------------------------------------------------------------------
                        10.00   10.00   clock clk (rise edge)
                         0.00   10.00   clock source latency
                 0.00    0.00   10.00 ^ clk (in)
    2    2.65                           clk (net)
                 0.00    0.00   10.00 ^ r1/CK (DFFR_X1)
                 0.01    0.10   10.10 ^ r1/Q (DFFR_X1)
    1    1.28                           r1q (net)
                 0.01    0.00   10.10 ^ u1/A (BUF_X1)
                 0.00    0.02   10.12 ^ u1/Z (BUF_X1)
    1    0.10                           data_out (net)
                 0.00    0.00   10.12 ^ data_out (out)
                                10.12   data arrival time

                        20.00   20.00   clock clk_gen (rise edge)
                         0.00   20.00   clock source latency
                 0.00    0.00   20.00 ^ clk (in)
    2    2.65                           clk (net)
                 0.00    0.00   20.00 ^ r2/CK (DFFR_X1)
                 0.01    0.10   20.10 ^ r2/Q (DFFR_X1)
    1    1.09                           clk_gen (net)
                 0.01    0.00   20.10 ^ u2/A (CLKBUF_X1)
                 0.01    0.02   20.12 ^ u2/Z (CLKBUF_X1)
    1    0.10                           clk_out (net)
                 0.01    0.00   20.12 ^ clk_out (out)
                         0.00   20.12   clock reconvergence pessimism
                        -7.00   13.12   output external delay
                                13.12   data required time
----------------------------------------------------------------------------
                                13.12   data required time
                               -10.12   data arrival time
----------------------------------------------------------------------------
                                 3.01   slack (MET)

Is there something wrong with my constraints or is it a bug for the unconstrained checks ? Thanks

The-OpenROAD-Project / OpenSTA

constrained output with reference pin gets marked as unconstrained #56