Parse Verilog attribute comments

[byzantic]

First of all, congrats on a really great tool!

I had a minor niggle when timing the output of blocks synthesised with Yosys. Yosys inserts attributes into the verilog to indicate the source files used, typically something like (* src multiplier.v:1 *)

OpenSTA does not recognise these, and so fails. OK, it's pretty straightforward to use awk or sed to remove these, so it's not a big problem. However, I did have a quick look in the lexer sources, and crowbar'ed the following into VerilogLex.ll, effectively creating another type of comment block.

%x ATTRIBUTE

"(*"    { BEGIN ATTRIBUTE; }
<ATTRIBUTE>{
.

{EOL}   { sta::verilog_reader->incrLine(); }

"*)"    { BEGIN INITIAL; }

<<EOF>> {
    VerilogParse_error("unterminated attribute");
    BEGIN(INITIAL);
    yyterminate();
    }
}

Seems to work OK ..

[jjcherry56]

can you attach a small verilog example from yosys showing the attributes in context that I can add to the regression?

[byzantic]

Hi James, here is the output of Yosys from a very simple test file that generates an AND gate. The OSU018 library was used as the target cell library

/* Generated by Yosys 0.8 (git sha1 5706e908, clang 6.0.0-1ubuntu2 -fPIC -Os) */

(* src = "tinygate.v:1" *)
module tinygate(a, b, z);
  wire _0_;
  wire _1_;
  wire _2_;
  (* src = "tinygate.v:3" *)
  input a;
  (* src = "tinygate.v:4" *)
  input b;
  (* src = "tinygate.v:5" *)
  output z;
  AND2X1 _3_ (
    .A(_0_),
    .B(_1_),
    .Y(_2_)
  );
  assign _0_ = b;
  assign _1_ = a;
  assign z = _2_;
endmodule

Ahem. Subsequent reading of the manual shows that Yosys can write out verilog without attributes (flag -noattr), or have them emitted as comments instead (flag -attr2comment). (Hangs head in shame ..)

[jjcherry56]

No shame required. If it is part of structural verilog, OpenSTA should be able to parse it without barfing.

On Monday, November 12, 2018, byzantic notifications@github.com wrote:

Hi James, here is the output of Yosys from a very simple test file that generates an AND gate. The OSU018 library was used as the target cell library

/ Generated by Yosys 0.8 (git sha1 5706e908, clang 6.0.0-1ubuntu2 -fPIC -Os) /

( src = "tinygate.v:1" ) module tinygate(a, b, z); wire 0; wire 1; wire 2; ( src = "tinygate.v:3" ) input a; ( src = "tinygate.v:4" ) input b; ( src = "tinygate.v:5" ) output z; AND2X1 3 ( .A(0), .B(1), .Y(2) ); assign 0 = b; assign 1 = a; assign z = 2; endmodule

Ahem. Subsequent reading of the manual shows that Yosys can write out verilog without attributes (flag -noattr), or have them emitted as comments instead (flag -attr2comment). (Hangs head in shame ..)

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