VerilogWriter.cc: write assign statements

[tgingold]

Assign statements are written for output ports when they are connected to a net whose name is not the name of the port.

This happen naturally when a cell is connected to more than one output ports, like in this reproducer extracted from a larger design:

module top(A, X1, X2); input A; output X1, X2; wire w;

mybuf buf1(.A(A), .X(w)); assign X1 = w; assign X2 = w; endmodule

If read and written with this change using these tcl commands:

read_verilog verilog1.v link_design top write_verilog t1.v

The verilog written is:

module top (A, X1, X2); input A; output X1; output X2;

mybuf buf1 (.A(A), .X(w)); assign X2 = w; assign X1 = w; endmodule

Without the assign statements, the written verilog is not equivalent to the read verilog. For ports other than output, additional work is needed (like adding trans gates), but I have not yet found a real example.

[jjcherry56]

this functionality was added by 46a835a5 master origin/master write_verilog assigns for nets with multiple output ports