syntax error, unexpected REG

[mdzakirhussain]

Why is that, sta reports this error "syntax error, unexpected REG".

I have synthesized using yosys, and the netlist file when read in sta, I am facing the aforesaid issue.

[jjcherry56]

Please provide a testcase that reproduces the issue.

[mdzakirhussain]

alu.txt fa.txt rca.txt tb.txt

[mdzakirhussain]

top module is alu.txt

[jjcherry56]

That is an RTL verilog. OpenSTA can only read structural verilog (post synthesis).

[mdzakirhussain]

i just provided the files

[jjcherry56]

For future reference, a text file containing verilog is not a testcase. There is no library data or tcl command file.

[mdzakirhussain]

synth.txt

[mdzakirhussain]

This is the file, after synthesis which I am using in opensta. Verilog files , .v is not getting uploaded so I uploaded txt files

[mdzakirhussain]

I am sorry for my ignorance. Please help me.

[mdzakirhussain]

sky130_fd_sc_hd__tt_025C_1v80.txt

I am using sky130_fd_sc_hd__tt_025C_1v80.lib

[jjcherry56]

synth.v/txt is not structural verilog. it has reg and always statements in it.