Closed kareefardi closed 2 years ago
Attached is a testcase that contains verilog files, liberty files, and sta.tcl cmd file. testcase.tar.gz
sta.tcl
It is a stack overflow trying to levelize the design. OpenSTA does not support unprogrammed fpga structures riddled with combinational logic loops.
Attached is a testcase that contains verilog files, liberty files, and
sta.tcl
cmd file. testcase.tar.gz