# cd alpha-release/flow
# make DESIGN_CONFIG=`pwd`/designs/tiny-tests.mk DESIGN_NAME=MuxTest_width_1_inputs_1_outputs_1_pipeline_5
[deleted]
/openroad/OpenROAD-2019-08-09_16-17/TritonCTS/bin/lefdef2cts -lef /data/objects/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_5/merged_padded.lef -def /data/results/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_5/3_place.def -cpin CK -cts sinks.txt -blk blks.txt
Running GH-tree (should take a while...)
/openroad/OpenROAD-2019-08-09_16-17/TritonCTS/bin/genHtree -n 64 -s 50 -tech 45 -compute_sink_region_mode -t 1000
Traceback (most recent call last):
File "./update_def.py", line 108, in <module>
readNetlistFile()
File "./update_def.py", line 59, in readNetlistFile
nets[terms[1]].append([instPinPair[0], instPinPair[1]])
IndexError: list index out of range
while executing
"exec ./update_def.py > cts.def "
(procedure "updateDEFAndVerilog" line 10)
invoked from within
"updateDEFAndVerilog"
(file "/openroad/OpenROAD-2019-08-09_16-17/TritonCTS/runTritonCTS.tcl" line 385)
make: *** [results/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_5/4_cts.v] Error 1
To reproduce, check out latest alpha-release: