search

The-OpenROAD-Project / alpha-release

Builds, flow and designs for the alpha release
Other
53 stars 17 forks source link

tests: added three test cases in regards to top-level pin-count #28

Closed oharboe closed 5 years ago

oharboe commented 5 years ago

These all fail in some way.

mgwoo commented 5 years ago

'clk' is mismatched with 'clock' in sdc and Verilog. Could you fix these issues and send a PR again?

tajayi commented 5 years ago

I recently added the ability to specify toplevel parameters see #12. Perhaps this can reduce the need for multiple verilog sources (and folders in src)? If that doesn't suite you, we can just put all the verilog files in a single pin-count folder in src and make multiple mk files for them

Also can you please add a README file to the "src" folder. You can reference aes or others that have been updated. It should mostly provide information on the history and intent of the design

For now, our "unit" tests are intended to go through the entire flow. I'm a bit concerned about the LargePinCount.v that is empty. It's likely that the downstream tools will barf while trying to run cts or route a completley empty design.

oharboe commented 5 years ago

My experience is that for a test system to succeed, it must be trivial to add tests: plonk in a single top level Verilog file and you're done.

What we're missing are testing directives in the comment section of the Verilog file.

The most important is to be able to specify that the build should fail and a regexp for the expected error message in the log.