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The-OpenROAD-Project / alpha-release

Builds, flow and designs for the alpha release
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Add Western Digital SWERV as test bench #6

Closed mithro closed 5 years ago

mithro commented 5 years ago

It would be awesome to add Western Digital SWERV RISC-V core as a test bench. You can find it at https://github.com/westerndigitalcorporation/swerv_eh1 and it is released under an Apache 2.0 license.

Western Digital’s RISC-V SweRV core is a 32-bit in-order core featuring a 2-way superscalar design and a nine-stage pipeline. When implemented using a 28 nm process technology, the core runs at up to 1.8 GHz. As for simulated performance, the SweRV core delivers 4.9 CoreMark/MHz, which is a bit higher when compared to ARM’s Cortex-A15. Western Digital will use its RISC-V cores for its own embedded designs, such as flash controllers and SSDs.

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Only issue is SWERV is just a CPU core and not a whole SoC?

tajayi commented 5 years ago

Thanks Tim. We'll try to queue this up

tajayi commented 5 years ago

swerv is also now running through the flow. I still need to do some characterization on it

ZvonimirBandic commented 5 years ago

wow, this is really awesome! Tim told me today in email, I was not aware. I am interested to learn more about this, and potentially reproduce what you are doing. Let me know if you found out any issues.

tajayi commented 5 years ago

Swerv is now mostly functional through the flow on 2 platforms. There are some DRCs issues that will hopefully be resolved by on-going efforts around DRCs and QoR.

swerv_nangate45 517 Viols Placement Density:9.75%(196620/2016361)

swerv_tsmc65lp 30 Viols. Placement Density:37.97%(762620/2008285)

swerv_wrapper_tsmc65lp 43 Viols. Placement Density:41.69%(789823/1894629) Several connectivity issues: Narrow Channels (Placement), Missing std cell rails

ZvonimirBandic commented 5 years ago

THANKS!

On Mon, Sep 9, 2019 at 11:13 AM Tutu Ajayi notifications@github.com wrote:

Swerv is now mostly functional through the flow on 2 platforms. There are some DRCs issues that will hopefully be resolved by on-going efforts around DRCs and QoR.

swerv_nangate45 517 Viols Placement Density:9.75%(196620/2016361)

swerv_tsmc65lp 30 Viols. Placement Density:37.97%(762620/2008285)

swerv_wrapper_tsmc65lp 43 Viols. Placement Density:41.69%(789823/1894629) Several connectivity issues: Narrow Channels (Placement), Missing std cell rails

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