Open efferto opened 3 years ago
@tspyrou who handles asap7 .lib issues?
We are aware of issues with the timing information for the integrated clock-gater (ICG) cells and asynchronous flip-flop. We were not aware of any issues related to SDFL and SDFH cells, but we will take a look. Thank you for bringing up these issues. We will try to address them in a subsequent release. Since we are not using any Synopsys tools, if the issues that you see persist despite our having fixed what we believe are problems in the ICG and ASYNC FF characterization, we will be unable to help. I hope you understand.
Dear @vvashish,
thanks for your reply. I recall that in the asap7PDK_r1p5 there were no issues in converting .lib in .db with Synopsys. I hope this could help. Without the possibility to use sequential blocks restrict the usage to only combinational circuits...
Dear @efferto,
Thank you for your helpful feedback. We will compare the changes that we made to the characterization flow.
Thanks @vvashish, having this fix on the sequential blocks would really useful (if something comes out from the diff). I can do the test on synopsys if needed.
Dear @vvashish,
thanks for your reply. I recall that in the asap7PDK_r1p5 there were no issues in converting .lib in .db with Synopsys. I hope this could help. Without the possibility to use sequential blocks restrict the usage to only combinational circuits...
Dear @vvashish,
thanks for your reply. I recall that in the asap7PDK_r1p5 there were no issues in converting .lib in .db with Synopsys. I hope this could help. Without the possibility to use sequential blocks restrict the usage to only combinational circuits...
there is no .lib in asap7PDK_r1p7. Another problem is that we can't compile the .db successfully.
Hello,
I'm converting .lib files to .db with lc_shell. Everything got converted except for SEQ modules for both timing models (NLDM and CCS). An example of error in the following: