Floorplan check_setup complains about unconstrained pins

[jeffng-or]

Floorplan check_setup

Warning: There are 148 input ports missing set_input_delay. Warning: There are 238 output ports missing set_output_delay. Warning: There are 676 unconstrained endpoints.

[oharboe]

Yes: this is intentional, we specifically dont want set_input/_output_delay and set_max_delay on pins dont count as "constrained" (why not???).

[jeffng-or]

@maliberty FYI since it came up when looking through the timing reports.

[oharboe]

@tspyrou I consider these pins constrained by set_max_delay, but OpenSTA doesnt. Thoughts?

[maliberty]

I understand your IO constraint methodology when you are doing a sub-block. I don't see why at the top level you don't want normal constraints.

[oharboe]

I understand your IO constraint methodology when you are doing a sub-block. I don't see why at the top level you don't want normal constraints.

BoomTile (MegaBoom) is not the top. It connect to a system bus and the system bus is running at the core clock. The system bus is ultimately connected to an asynchronous clock crossing bridge(to connect to peripheral bridges, DRAM, etc.)

So: the timing tools for making this chip has reg2reg paths all the way to the async FIFO, there are no set_input/output_delay constraints before the async FIFO.

set_input/output_delay is only used at the top level on the pins of the chip. There is an asynchronous bridge between the inside of the chip and the external pins and the clock tree latency on the pin side is very shallow.

This is represented in the designs/asap7/mock-cpu example design. Those .sdc files could do with some more sophistication, but essentially that is what is going on. The .sdc files were written before the post-synthesis variable names in verilog were stable.