Closed oharboe closed 2 months ago
@maliberty @tspyrou @lpawelcz Much better:
While the fMax is not impressive, it is in the expected range at this point, 7000ps.
mpl2 doesn't work with flattening in yosys.
The MegaBoom design requires flattening, register retiming & cloning, after which it can get to just under 1000ps at 28nm:
mock SRAMs after floorplan have pathological timing
This should fix the pathological slack seen here in the clock tree. The macros is the right branch of the clock tree and the clock tree should end roughly horizontal for all elements(as little slack as possible):