Verilator

[mkosunen]

@Roenski I do not know how much you have worked on this already, but this branch contains a minimum working example of inverter simulation with verilator. It is

Currently simulation is not executed from python, but by by executing ./configure && make verilator . configure is the documentation of the command calls.

The testbench file sim_main.cpp contains the minimum set of additional variable definitions, verilator function calls, and vcd dump.

Objectives.

1. Transfer the simulator calls to rtl package
2. Implement the testbench generation in rtl/testbench package.

Eventually these two branches will be merged to RC_1.9 development branch in a state were the verilog simulation with verilator can be run as a standard TheSyDeKick simulation, including interactive mode.

[mkosunen]

I see that you are well under way with the rtl entity. Let's keep this here until it is done.

[Roenski]

I have been trying to make the testbench generator in a similar way to the current one for (system)verilog. So, this code does not overlap my work in any way.

[Roenski]

Ah this was a merge request for verilator branch. Yes, for now it's easier to keep them separated and merge (or altogether replace) once the verilog rtl-entity works.