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TheSystemDevelopmentKit / inverter

This is a very simple example of a TheSDK Entity submodule
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VHDL output shifted by 1 #22

Closed Roenski closed 1 year ago

Roenski commented 1 year ago

@mkosunen

In v1.9_RC branch:

VHDL output in the plot is shifted by one.

Can be fixed by using a negedge as trigger like in sv and icarus models, or adding a latency in the plotter.

image

mkosunen commented 1 year ago

Fixed in #21 Closed by a59d7d09fe22dcd