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TheSystemDevelopmentKit / inverter

This is a very simple example of a TheSDK Entity submodule
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Test setup for vhdl_testbench #23

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

This PR contains modificatiosn needed to support VHDL-onlysimulations with VHDL testbench of RTL entity.

mkosunen commented 1 year ago

Related to https://github.com/TheSystemDevelopmentKit/rtl/pull/51

Ping @Roenski