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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Optimize set_control_data #12

Closed mkosunen closed 3 years ago

mkosunen commented 3 years ago

I already merged this after throughly testing it (I thought). However, it seems that it breaks Non event-based IO's. Try to run inverter sv sim with it.

@chiplet

mkosunen commented 3 years ago

@chiplet I think now it works. Can you confirm?

chiplet commented 3 years ago

@mkosunen JTAG programming in simulation still works after these changes. 👍

When running the sv model for the inv_sim entity I can see a delay of one cycle. Should this happen? This behaviour doesn't seem to depend on the changes in this PR though as reverting to the preceding rtl commit still shows the one cycle delay.

Screenshot 2021-08-11 at 12 13 27

mkosunen commented 3 years ago

Thatis controlled with the 'latency' vector in main guard. For rtl simulations, latency should be 1 as file IO is syncronous to clock. This is ugly, but most of the designs are syncronous anyway. Asychronous inverter is an exception.

mkosunen commented 3 years ago

I'l' merge this anyway as I see it is clear and good. Let's handle that spice feature independently.