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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Add rtl_timeunit property #19

Closed mkosunen closed 2 years ago

mkosunen commented 2 years ago

By default, simulator is invoked with 1ps time unit. This should be controllable.

mkosunen commented 2 years ago

Added as rtl_timescale with commit fd312f30f8