Add suport for mixed mode compilation for Questa

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control

Other

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Closed mkosunen closed 2 years ago

mkosunen commented 2 years ago

Goal: Enable mixed mode simulations with questa

VHDL modules are now compiled in sv mode before testbench compilation

mkosunen commented 2 years ago

Note: Not ready to merge, we should not hardcode the VHDL version. It should be a property.