Add support for Icarus Verilog

[Roenski]

Add support for running RTL simulation with Icarus Verilog.

The easiest way to dev this is to clone the template project. and use the inverter example. There's also the tutorial to get you started. Once you get it working, you can try with A-Core and run some simulation that prints something (e.g. sim_mem_tests or hello world).

Rtl entity handles calling the RTL simulator. The place where rtl command is generated is the rtlcmd property method in __init__.py. You should add a command for running Icarus Verilog there. We decided that, for now, the simplest way is to add a new model (e.g. icarus) to self.model and select the correct rtl command with that. Note that Icarus cannot run VHDL, so you only need to copy the functionality of Verilog-only compilation.

The simulation should also dump a .vcd waveform file, see if it does it automatically or whether some argument is needed.

There's also the interactive_rtl property, which selects whether the waveform is displayed after simulation. At first, you can just ignore that property when running with Icarus, but if you still have time you can add support for GTKWave, I will create a separate issue about that.

Icarus version on our clusters is quite old (10.2, newest is 11.x) so there may have been some changes to the command line interface. We cannot update the cluster version now as Artturi is on holiday so let's stick to the 10.2 commands for now.

[Roenski]

Use the icarus branch for development.

[Roenski]

Done. Great job @Anttitarkka !