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TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control
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Add parameter word to testbench parameter list #33

Closed Roenski closed 2 years ago

Roenski commented 2 years ago

See issue https://github.com/TheSystemDevelopmentKit/rtl/issues/32

Roenski commented 2 years ago

It did not break anything in the template projetct so I suppose it can be merged