Add support for custom connectors

[Roenski]

Adds self.custom_connectors property, where the user can define a custom verilog_connector_bundle that will be updated to testbench connectors. Also adds self.add_custom_connectors() method to run_rtl(). Also, adds self.assignment_matchlist to rtl level. It used to reside in testbench, but I could not figure out a proper way to add it nicely from DUT side when using only that structure.

This modification allows connecting IOFile signals to internal signals. I used this structure to connect an internal register signal ACoreChip.core.regfile_block.regfile.x_10 to an IOFile signal a0. The register contents get stored into the file.

[Roenski]

@mkosunen Does this look alright to you?

Also, I was thinking what is the point of assignment_matchlist ? Before this MR, it resides only in TB, so you couldn't edit it from outside rtl. There is a keyword argument matchlist but it cannot be propagated from anywhere. But, my main point was, Why wouldn't you just connect everything by default? It seems a bit redundant to first specify a .connect property, and then re-state that you also want to connect it.

Example case from A-Core:

self.dut.custom_connectors = verilog_connector_bundle()
self.dut.custom_connectors.Members['a0'] = verilog_connector(name='a0', cls='wire')
self.dut.custom_connectors.Members['mstopsim'] = verilog_connector(name='mstopsim', cls='wire')
self.dut.custom_connectors.Members['ACoreChip.core.csreg_block.csregs.mstopsim'] = verilog_connector(name='ACoreChip.core.csreg_block.csregs.mstopsim')
self.dut.custom_connectors.Members['ACoreChip.core.regfile_block.regfile.x_10'] = verilog_connector(name='ACoreChip.core.regfile_block.regfile.x_10')
self.dut.custom_connectors.Members['mstopsim'].connect = self.dut.custom_connectors.Members['ACoreChip.core.csreg_block.csregs.mstopsim']
self.dut.custom_connectors.Members['a0'].connect = self.dut.custom_connectors.Members['ACoreChip.core.regfile_block.regfile.x_10']
self.dut.assignment_matchlist = ['mstopsim', 'a0']